0af312b6ed
This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size). Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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.. | ||
aspeed.rst | ||
collie.rst | ||
cpu-features.rst | ||
cubieboard.rst | ||
digic.rst | ||
emcraft-sf2.rst | ||
emulation.rst | ||
gumstix.rst | ||
highbank.rst | ||
imx25-pdk.rst | ||
integratorcp.rst | ||
kzm.rst | ||
mainstone.rst | ||
mps2.rst | ||
musca.rst | ||
musicpal.rst | ||
nrf.rst | ||
nseries.rst | ||
nuvoton.rst | ||
orangepi.rst | ||
palm.rst | ||
raspi.rst | ||
realview.rst | ||
sabrelite.rst | ||
sbsa.rst | ||
stellaris.rst | ||
stm32.rst | ||
sx1.rst | ||
versatile.rst | ||
vexpress.rst | ||
virt.rst | ||
xlnx-versal-virt.rst | ||
xscale.rst |