Jonathan Cameron bfc2f7a6ca hw/cxl: Fix missing reserved data in CXL Device DVSEC ... The r3.1 specification introduced a new 2 byte field, but to maintain DWORD alignment, a additional 2 reserved bytes were added. Forgot those in updating the structure definition but did include them in the size define leading to a buffer overrun. Also use the define so that we don't duplicate the value. Fixes: Coverity ID 1534095 buffer overrun Fixes: 8700ee15de ("hw/cxl: Standardize all references on CXL r3.1 and minor updates") Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240308143831.6256-1-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2024-03-12 17:59:48 -04:00
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cxl_cdat.h	hw/mem/cxl_type3: Fix problem with g_steal_pointer()	2024-03-09 18:56:37 +03:00
cxl_component.h	hw/pci-bridge/pxb-cxl: Drop RAS capability from host bridge.	2024-03-12 17:56:55 -04:00
cxl_device.h	hw/cxl/cxl_device.h: correct typos	2024-02-21 08:16:43 +03:00
cxl_events.h	hw/cxl: Standardize all references on CXL r3.1 and minor updates	2024-02-14 06:09:33 -05:00
cxl_host.h	hw/cxl: Clean up includes	2023-02-08 07:16:23 +01:00
cxl_pci.h	hw/cxl: Fix missing reserved data in CXL Device DVSEC	2024-03-12 17:59:48 -04:00
cxl.h	hw/cxl/mbox: Add Physical Switch Identify command.	2023-11-07 03:39:11 -05:00