qemu-e2k/target-tricore
Bastian Koppelmann 0b79a78169 target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode
Add instructions of RR opcode format, that have 0xf as the first opcode.
Add helper functions:
    * clo/z/s: Counts leading ones/zeros/signs.
    * clo/z/s_h: Count leading ones/zeros/signs in two haflwords.
    * sh/_h: Shifts one/two word/hwords.
    * sha/_h: Shifts one/two word/hwords arithmeticly.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:34:48 +00:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: Make TRICORE_FEATURES implying others. 2014-12-10 11:13:45 +00:00
cpu.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
csfr.def target-tricore: Add instructions of RLC opcode format 2014-12-10 11:13:45 +00:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode 2014-12-21 18:34:48 +00:00
Makefile.objs
op_helper.c target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode 2014-12-21 18:34:48 +00:00
translate.c target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode 2014-12-21 18:34:48 +00:00
tricore-defs.h
tricore-opcodes.h target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode 2014-12-21 18:34:34 +00:00