600 lines
16 KiB
C
600 lines
16 KiB
C
/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h"
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#include "pc.h"
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#include "apm.h"
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#include "pm_smbus.h"
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#include "pci.h"
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#include "acpi.h"
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//#define DEBUG
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#ifdef DEBUG
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# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define PIIX4_DPRINTF(format, ...) do { } while (0)
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#endif
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#define ACPI_DBG_IO_ADDR 0xb044
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#define GPE_BASE 0xafe0
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#define PCI_BASE 0xae00
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#define PCI_EJ_BASE 0xae08
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struct gpe_regs {
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uint16_t sts; /* status */
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uint16_t en; /* enabled */
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};
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struct pci_status {
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uint32_t up;
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uint32_t down;
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};
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typedef struct PIIX4PMState {
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PCIDevice dev;
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uint16_t pmsts;
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uint16_t pmen;
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uint16_t pmcntrl;
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APMState apm;
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QEMUTimer *tmr_timer;
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int64_t tmr_overflow_time;
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PMSMBus smb;
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uint32_t smb_io_base;
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qemu_irq irq;
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qemu_irq cmos_s3;
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qemu_irq smi_irq;
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int kvm_enabled;
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/* for pci hotplug */
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struct gpe_regs gpe;
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struct pci_status pci0_status;
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} PIIX4PMState;
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static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
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#define ACPI_ENABLE 0xf1
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#define ACPI_DISABLE 0xf0
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{
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uint32_t d;
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
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return d & 0xffffff;
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}
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static int get_pmsts(PIIX4PMState *s)
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{
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int64_t d;
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
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get_ticks_per_sec());
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if (d >= s->tmr_overflow_time)
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s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
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return s->pmsts;
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}
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static void pm_update_sci(PIIX4PMState *s)
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{
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int sci_level, pmsts;
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int64_t expire_time;
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pmsts = get_pmsts(s);
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sci_level = (((pmsts & s->pmen) &
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(ACPI_BITMASK_RT_CLOCK_ENABLE |
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ACPI_BITMASK_POWER_BUTTON_ENABLE |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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ACPI_BITMASK_TIMER_ENABLE)) != 0);
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qemu_set_irq(s->irq, sci_level);
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/* schedule a timer interruption if needed */
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if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
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!(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
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expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
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PM_TIMER_FREQUENCY);
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qemu_mod_timer(s->tmr_timer, expire_time);
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} else {
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qemu_del_timer(s->tmr_timer);
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}
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}
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static void pm_tmr_timer(void *opaque)
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{
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PIIX4PMState *s = opaque;
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pm_update_sci(s);
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}
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4PMState *s = opaque;
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addr &= 0x3f;
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switch(addr) {
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case 0x00:
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{
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int64_t d;
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int pmsts;
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pmsts = get_pmsts(s);
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if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
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get_ticks_per_sec());
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
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}
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s->pmsts &= ~val;
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pm_update_sci(s);
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}
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break;
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case 0x02:
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s->pmen = val;
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pm_update_sci(s);
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break;
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case 0x04:
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{
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int sus_typ;
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s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
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if (val & ACPI_BITMASK_SLEEP_ENABLE) {
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/* change suspend type */
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sus_typ = (val >> 10) & 7;
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switch(sus_typ) {
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case 0: /* soft power off */
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qemu_system_shutdown_request();
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break;
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case 1:
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/* ACPI_BITMASK_WAKE_STATUS should be set on resume.
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Pretend that resume was caused by power button */
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s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
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ACPI_BITMASK_POWER_BUTTON_STATUS);
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qemu_system_reset_request();
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if (s->cmos_s3) {
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qemu_irq_raise(s->cmos_s3);
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}
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default:
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break;
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}
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}
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}
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break;
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default:
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break;
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}
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PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
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}
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case 0x00:
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val = get_pmsts(s);
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break;
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case 0x02:
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val = s->pmen;
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break;
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case 0x04:
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val = s->pmcntrl;
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break;
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default:
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val = 0;
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break;
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}
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PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
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return val;
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}
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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// PIIX4PMState *s = opaque;
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PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val);
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}
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
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{
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PIIX4PMState *s = opaque;
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uint32_t val;
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addr &= 0x3f;
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switch(addr) {
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case 0x08:
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val = get_pmtmr(s);
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break;
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default:
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val = 0;
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break;
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}
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PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
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return val;
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}
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static void apm_ctrl_changed(uint32_t val, void *arg)
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{
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PIIX4PMState *s = arg;
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/* ACPI specs 3.0, 4.7.2.5 */
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if (val == ACPI_ENABLE) {
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s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
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} else if (val == ACPI_DISABLE) {
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s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
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}
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if (s->dev.config[0x5b] & (1 << 1)) {
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if (s->smi_irq) {
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qemu_irq_raise(s->smi_irq);
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}
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}
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}
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
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{
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PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
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}
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static void pm_io_space_update(PIIX4PMState *s)
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{
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uint32_t pm_io_base;
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if (s->dev.config[0x80] & 1) {
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pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
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pm_io_base &= 0xffc0;
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/* XXX: need to improve memory and ioport allocation */
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PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
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register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
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register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
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register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
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register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
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}
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}
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static void pm_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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pci_default_write_config(d, address, val, len);
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if (range_covers_byte(address, len, 0x80))
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pm_io_space_update((PIIX4PMState *)d);
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}
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static int vmstate_acpi_post_load(void *opaque, int version_id)
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{
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PIIX4PMState *s = opaque;
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pm_io_space_update(s);
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return 0;
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}
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static const VMStateDescription vmstate_acpi = {
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.name = "piix4_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
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VMSTATE_UINT16(pmsts, PIIX4PMState),
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VMSTATE_UINT16(pmen, PIIX4PMState),
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VMSTATE_UINT16(pmcntrl, PIIX4PMState),
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VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
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VMSTATE_TIMER(tmr_timer, PIIX4PMState),
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VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void piix4_reset(void *opaque)
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{
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PIIX4PMState *s = opaque;
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uint8_t *pci_conf = s->dev.config;
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pci_conf[0x58] = 0;
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pci_conf[0x59] = 0;
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pci_conf[0x5a] = 0;
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pci_conf[0x5b] = 0;
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if (s->kvm_enabled) {
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/* Mark SMM as already inited (until KVM supports SMM). */
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pci_conf[0x5B] = 0x02;
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}
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}
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static void piix4_powerdown(void *opaque, int irq, int power_failing)
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{
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PIIX4PMState *s = opaque;
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if (!s) {
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qemu_system_shutdown_request();
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} else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
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s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
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pm_update_sci(s);
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}
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}
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static int piix4_pm_initfn(PCIDevice *dev)
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{
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PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
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uint8_t *pci_conf;
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pci_conf = s->dev.config;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
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pci_conf[0x06] = 0x80;
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pci_conf[0x07] = 0x02;
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pci_conf[0x08] = 0x03; // revision number
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pci_conf[0x09] = 0x00;
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pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
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pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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pci_conf[0x3d] = 0x01; // interrupt pin 1
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pci_conf[0x40] = 0x01; /* PM io base read only bit */
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/* APM */
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apm_init(&s->apm, apm_ctrl_changed, s);
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register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
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if (s->kvm_enabled) {
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/* Mark SMM as already inited to prevent SMM from running. KVM does not
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* support SMM mode. */
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pci_conf[0x5B] = 0x02;
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}
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/* XXX: which specification is used ? The i82731AB has different
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mappings */
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pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
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pci_conf[0x63] = 0x60;
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pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
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(serial_hds[1] != NULL ? 0x90 : 0);
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pci_conf[0x90] = s->smb_io_base | 1;
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pci_conf[0x91] = s->smb_io_base >> 8;
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pci_conf[0xd2] = 0x09;
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register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
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register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
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s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
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qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
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pm_smbus_init(&s->dev.qdev, &s->smb);
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qemu_register_reset(piix4_reset, s);
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piix4_acpi_system_hot_add_init(dev->bus, s);
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return 0;
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}
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
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int kvm_enabled)
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{
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PCIDevice *dev;
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PIIX4PMState *s;
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dev = pci_create(bus, devfn, "PIIX4_PM");
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qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
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s = DO_UPCAST(PIIX4PMState, dev, dev);
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s->irq = sci_irq;
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s->cmos_s3 = cmos_s3;
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s->smi_irq = smi_irq;
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s->kvm_enabled = kvm_enabled;
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qdev_init_nofail(&dev->qdev);
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return s->smb.smbus;
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}
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static PCIDeviceInfo piix4_pm_info = {
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.qdev.name = "PIIX4_PM",
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.qdev.desc = "PM",
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.qdev.size = sizeof(PIIX4PMState),
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.qdev.vmsd = &vmstate_acpi,
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.init = piix4_pm_initfn,
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.config_write = pm_write_config,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void piix4_pm_register(void)
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{
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pci_qdev_register(&piix4_pm_info);
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}
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device_init(piix4_pm_register);
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static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
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{
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if (addr & 1)
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return (val >> 8) & 0xff;
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return val & 0xff;
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}
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static uint32_t gpe_readb(void *opaque, uint32_t addr)
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{
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uint32_t val = 0;
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struct gpe_regs *g = opaque;
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switch (addr) {
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case GPE_BASE:
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case GPE_BASE + 1:
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val = gpe_read_val(g->sts, addr);
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break;
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case GPE_BASE + 2:
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case GPE_BASE + 3:
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val = gpe_read_val(g->en, addr);
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break;
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default:
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break;
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}
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PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
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return val;
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}
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static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
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{
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if (addr & 1)
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*cur = (*cur & 0xff) | (val << 8);
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else
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*cur = (*cur & 0xff00) | (val & 0xff);
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}
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static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
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{
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uint16_t x1, x0 = val & 0xff;
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int shift = (addr & 1) ? 8 : 0;
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x1 = (*cur >> shift) & 0xff;
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x1 = x1 & ~x0;
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*cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
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}
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static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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struct gpe_regs *g = opaque;
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switch (addr) {
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case GPE_BASE:
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case GPE_BASE + 1:
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gpe_reset_val(&g->sts, addr, val);
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break;
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case GPE_BASE + 2:
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case GPE_BASE + 3:
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gpe_write_val(&g->en, addr, val);
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break;
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default:
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break;
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}
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PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
|
|
}
|
|
|
|
static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
|
|
{
|
|
uint32_t val = 0;
|
|
struct pci_status *g = opaque;
|
|
switch (addr) {
|
|
case PCI_BASE:
|
|
val = g->up;
|
|
break;
|
|
case PCI_BASE + 4:
|
|
val = g->down;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
|
|
return val;
|
|
}
|
|
|
|
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
struct pci_status *g = opaque;
|
|
switch (addr) {
|
|
case PCI_BASE:
|
|
g->up = val;
|
|
break;
|
|
case PCI_BASE + 4:
|
|
g->down = val;
|
|
break;
|
|
}
|
|
|
|
PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
|
|
}
|
|
|
|
static uint32_t pciej_read(void *opaque, uint32_t addr)
|
|
{
|
|
PIIX4_DPRINTF("pciej read %x\n", addr);
|
|
return 0;
|
|
}
|
|
|
|
static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
BusState *bus = opaque;
|
|
DeviceState *qdev, *next;
|
|
PCIDevice *dev;
|
|
int slot = ffs(val) - 1;
|
|
|
|
QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
|
|
dev = DO_UPCAST(PCIDevice, qdev, qdev);
|
|
if (PCI_SLOT(dev->devfn) == slot) {
|
|
qdev_free(qdev);
|
|
}
|
|
}
|
|
|
|
|
|
PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
|
|
}
|
|
|
|
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state);
|
|
|
|
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
|
|
{
|
|
struct gpe_regs *gpe = &s->gpe;
|
|
struct pci_status *pci0_status = &s->pci0_status;
|
|
|
|
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe);
|
|
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, gpe);
|
|
|
|
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
|
|
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status);
|
|
|
|
register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
|
|
register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus);
|
|
|
|
pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
|
|
}
|
|
|
|
static void enable_device(PIIX4PMState *s, int slot)
|
|
{
|
|
s->gpe.sts |= 2;
|
|
s->pci0_status.up |= (1 << slot);
|
|
}
|
|
|
|
static void disable_device(PIIX4PMState *s, int slot)
|
|
{
|
|
s->gpe.sts |= 2;
|
|
s->pci0_status.down |= (1 << slot);
|
|
}
|
|
|
|
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state)
|
|
{
|
|
int slot = PCI_SLOT(dev->devfn);
|
|
PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
|
|
DO_UPCAST(PCIDevice, qdev, qdev));
|
|
|
|
s->pci0_status.up = 0;
|
|
s->pci0_status.down = 0;
|
|
if (state) {
|
|
enable_device(s, slot);
|
|
} else {
|
|
disable_device(s, slot);
|
|
}
|
|
if (s->gpe.en & 2) {
|
|
qemu_set_irq(s->irq, 1);
|
|
qemu_set_irq(s->irq, 0);
|
|
}
|
|
return 0;
|
|
}
|