ce35e2295e
Move the property types and property macros implemented in qdev-properties-system.c to a new qdev-properties-system.h header. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20201211220529.2290218-16-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
286 lines
8.1 KiB
C
286 lines
8.1 KiB
C
/*
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* QEMU SiFive U OTP (One-Time Programmable) Memory interface
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*
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* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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*
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* Simple model of the OTP to emulate register reads made by the SDK BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "hw/sysbus.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/misc/sifive_u_otp.h"
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#include "sysemu/blockdev.h"
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#include "sysemu/block-backend.h"
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#define WRITTEN_BIT_ON 0x1
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#define SET_FUSEARRAY_BIT(map, i, off, bit) \
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map[i] = bit ? (map[i] | bit << off) : (map[i] & ~(0x1 << off))
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#define GET_FUSEARRAY_BIT(map, i, off) \
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((map[i] >> off) & 0x1)
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static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
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{
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SiFiveUOTPState *s = opaque;
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switch (addr) {
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case SIFIVE_U_OTP_PA:
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return s->pa;
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case SIFIVE_U_OTP_PAIO:
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return s->paio;
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case SIFIVE_U_OTP_PAS:
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return s->pas;
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case SIFIVE_U_OTP_PCE:
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return s->pce;
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case SIFIVE_U_OTP_PCLK:
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return s->pclk;
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case SIFIVE_U_OTP_PDIN:
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return s->pdin;
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case SIFIVE_U_OTP_PDOUT:
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if ((s->pce & SIFIVE_U_OTP_PCE_EN) &&
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(s->pdstb & SIFIVE_U_OTP_PDSTB_EN) &&
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(s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) {
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/* read from backend */
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if (s->blk) {
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int32_t buf;
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blk_pread(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD, &buf,
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SIFIVE_U_OTP_FUSE_WORD);
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return buf;
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}
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return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK];
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} else {
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return 0xff;
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}
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case SIFIVE_U_OTP_PDSTB:
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return s->pdstb;
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case SIFIVE_U_OTP_PPROG:
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return s->pprog;
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case SIFIVE_U_OTP_PTC:
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return s->ptc;
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case SIFIVE_U_OTP_PTM:
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return s->ptm;
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case SIFIVE_U_OTP_PTM_REP:
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return s->ptm_rep;
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case SIFIVE_U_OTP_PTR:
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return s->ptr;
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case SIFIVE_U_OTP_PTRIM:
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return s->ptrim;
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case SIFIVE_U_OTP_PWE:
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return s->pwe;
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}
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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static void sifive_u_otp_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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SiFiveUOTPState *s = opaque;
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uint32_t val32 = (uint32_t)val64;
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switch (addr) {
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case SIFIVE_U_OTP_PA:
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s->pa = val32 & SIFIVE_U_OTP_PA_MASK;
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break;
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case SIFIVE_U_OTP_PAIO:
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s->paio = val32;
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break;
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case SIFIVE_U_OTP_PAS:
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s->pas = val32;
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break;
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case SIFIVE_U_OTP_PCE:
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s->pce = val32;
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break;
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case SIFIVE_U_OTP_PCLK:
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s->pclk = val32;
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break;
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case SIFIVE_U_OTP_PDIN:
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s->pdin = val32;
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break;
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case SIFIVE_U_OTP_PDOUT:
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/* read-only */
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break;
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case SIFIVE_U_OTP_PDSTB:
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s->pdstb = val32;
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break;
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case SIFIVE_U_OTP_PPROG:
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s->pprog = val32;
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break;
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case SIFIVE_U_OTP_PTC:
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s->ptc = val32;
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break;
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case SIFIVE_U_OTP_PTM:
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s->ptm = val32;
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break;
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case SIFIVE_U_OTP_PTM_REP:
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s->ptm_rep = val32;
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break;
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case SIFIVE_U_OTP_PTR:
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s->ptr = val32;
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break;
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case SIFIVE_U_OTP_PTRIM:
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s->ptrim = val32;
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break;
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case SIFIVE_U_OTP_PWE:
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s->pwe = val32 & SIFIVE_U_OTP_PWE_EN;
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/* PWE is enabled. Ignore PAS=1 (no redundancy cell) */
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if (s->pwe && !s->pas) {
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if (GET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"write once error: idx<%u>, bit<%u>\n",
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s->pa, s->paio);
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break;
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}
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/* write bit data */
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SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin);
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/* write to backend */
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if (s->blk) {
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blk_pwrite(s->blk, s->pa * SIFIVE_U_OTP_FUSE_WORD,
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&s->fuse[s->pa], SIFIVE_U_OTP_FUSE_WORD, 0);
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}
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/* update written bit */
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SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio, WRITTEN_BIT_ON);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
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" v=0x%x\n", __func__, addr, val32);
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}
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}
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static const MemoryRegionOps sifive_u_otp_ops = {
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.read = sifive_u_otp_read,
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.write = sifive_u_otp_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static Property sifive_u_otp_properties[] = {
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DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0),
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DEFINE_PROP_DRIVE("drive", SiFiveUOTPState, blk),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
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{
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SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
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DriveInfo *dinfo;
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memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s,
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TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
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dinfo = drive_get_next(IF_NONE);
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if (dinfo) {
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int ret;
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uint64_t perm;
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int filesize;
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BlockBackend *blk;
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blk = blk_by_legacy_dinfo(dinfo);
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filesize = SIFIVE_U_OTP_NUM_FUSES * SIFIVE_U_OTP_FUSE_WORD;
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if (blk_getlength(blk) < filesize) {
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error_setg(errp, "OTP drive size < 16K");
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return;
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}
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qdev_prop_set_drive_err(dev, "drive", blk, errp);
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if (s->blk) {
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perm = BLK_PERM_CONSISTENT_READ |
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(blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE);
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ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
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if (ret < 0) {
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return;
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}
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if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
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error_setg(errp, "failed to read the initial flash content");
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}
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}
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}
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}
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static void sifive_u_otp_reset(DeviceState *dev)
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{
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SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
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/* Initialize all fuses' initial value to 0xFFs */
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memset(s->fuse, 0xff, sizeof(s->fuse));
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/* Make a valid content of serial number */
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s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial;
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s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial);
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if (s->blk) {
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/* Put serial number to backend as well*/
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uint32_t serial_data;
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int index = SIFIVE_U_OTP_SERIAL_ADDR;
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serial_data = s->serial;
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blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
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&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
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serial_data = ~(s->serial);
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blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
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&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0);
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}
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/* Initialize write-once map */
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memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo));
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}
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static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_props(dc, sifive_u_otp_properties);
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dc->realize = sifive_u_otp_realize;
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dc->reset = sifive_u_otp_reset;
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}
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static const TypeInfo sifive_u_otp_info = {
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.name = TYPE_SIFIVE_U_OTP,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SiFiveUOTPState),
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.class_init = sifive_u_otp_class_init,
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};
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static void sifive_u_otp_register_types(void)
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{
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type_register_static(&sifive_u_otp_info);
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}
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type_init(sifive_u_otp_register_types)
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