575 lines
20 KiB
C
575 lines
20 KiB
C
/*
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* ARM GICv3 support - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2012 Linaro Limited
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* Copyright (c) 2015 Huawei.
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* Written by Peter Maydell
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* Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/core/cpu.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "gicv3_internal.h"
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#include "hw/arm/linux-boot-if.h"
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#include "sysemu/kvm.h"
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static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)
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{
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if (cs->gicd_no_migration_shift_bug) {
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return;
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}
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/* Older versions of QEMU had a bug in the handling of state save/restore
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* to the KVM GICv3: they got the offset in the bitmap arrays wrong,
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* so that instead of the data for external interrupts 32 and up
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* starting at bit position 32 in the bitmap, it started at bit
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* position 64. If we're receiving data from a QEMU with that bug,
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* we must move the data down into the right place.
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*/
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memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8,
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sizeof(cs->group) - GIC_INTERNAL / 8);
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memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8,
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sizeof(cs->grpmod) - GIC_INTERNAL / 8);
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memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8,
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sizeof(cs->enabled) - GIC_INTERNAL / 8);
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memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8,
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sizeof(cs->pending) - GIC_INTERNAL / 8);
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memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8,
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sizeof(cs->active) - GIC_INTERNAL / 8);
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memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL / 8,
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sizeof(cs->edge_trigger) - GIC_INTERNAL / 8);
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/*
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* While this new version QEMU doesn't have this kind of bug as we fix it,
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* so it needs to set the flag to true to indicate that and it's necessary
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* for next migration to work from this new version QEMU.
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*/
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cs->gicd_no_migration_shift_bug = true;
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}
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static int gicv3_pre_save(void *opaque)
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{
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GICv3State *s = (GICv3State *)opaque;
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ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
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if (c->pre_save) {
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c->pre_save(s);
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}
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return 0;
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}
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static int gicv3_post_load(void *opaque, int version_id)
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{
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GICv3State *s = (GICv3State *)opaque;
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ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
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gicv3_gicd_no_migration_shift_bug_post_load(s);
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if (c->post_load) {
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c->post_load(s);
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}
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return 0;
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}
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static bool virt_state_needed(void *opaque)
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{
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GICv3CPUState *cs = opaque;
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return cs->num_list_regs != 0;
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}
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static const VMStateDescription vmstate_gicv3_cpu_virt = {
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.name = "arm_gicv3_cpu/virt",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = virt_state_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_2DARRAY(ich_apr, GICv3CPUState, 3, 4),
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VMSTATE_UINT64(ich_hcr_el2, GICv3CPUState),
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VMSTATE_UINT64_ARRAY(ich_lr_el2, GICv3CPUState, GICV3_LR_MAX),
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VMSTATE_UINT64(ich_vmcr_el2, GICv3CPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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static int vmstate_gicv3_cpu_pre_load(void *opaque)
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{
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GICv3CPUState *cs = opaque;
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/*
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* If the sre_el1 subsection is not transferred this
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* means SRE_EL1 is 0x7 (which might not be the same as
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* our reset value).
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*/
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cs->icc_sre_el1 = 0x7;
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return 0;
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}
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static bool icc_sre_el1_reg_needed(void *opaque)
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{
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GICv3CPUState *cs = opaque;
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return cs->icc_sre_el1 != 7;
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}
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const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
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.name = "arm_gicv3_cpu/sre_el1",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = icc_sre_el1_reg_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_gicv3_cpu = {
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.name = "arm_gicv3_cpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_load = vmstate_gicv3_cpu_pre_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(level, GICv3CPUState),
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VMSTATE_UINT32(gicr_ctlr, GICv3CPUState),
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VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2),
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VMSTATE_UINT32(gicr_waker, GICv3CPUState),
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VMSTATE_UINT64(gicr_propbaser, GICv3CPUState),
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VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState),
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VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState),
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VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState),
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VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState),
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VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState),
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VMSTATE_UINT32(edge_trigger, GICv3CPUState),
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VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState),
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VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
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VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL),
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VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2),
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VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState),
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VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3),
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VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4),
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VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3),
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VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription * []) {
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&vmstate_gicv3_cpu_virt,
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&vmstate_gicv3_cpu_sre_el1,
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NULL
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}
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};
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static int gicv3_pre_load(void *opaque)
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{
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GICv3State *cs = opaque;
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/*
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* The gicd_no_migration_shift_bug flag is used for migration compatibility
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* for old version QEMU which may have the GICD bmp shift bug under KVM mode.
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* Strictly, what we want to know is whether the migration source is using
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* KVM. Since we don't have any way to determine that, we look at whether the
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* destination is using KVM; this is close enough because for the older QEMU
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* versions with this bug KVM -> TCG migration didn't work anyway. If the
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* source is a newer QEMU without this bug it will transmit the migration
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* subsection which sets the flag to true; otherwise it will remain set to
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* the value we select here.
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*/
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if (kvm_enabled()) {
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cs->gicd_no_migration_shift_bug = false;
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}
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return 0;
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}
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static bool needed_always(void *opaque)
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{
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return true;
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}
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const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = {
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.name = "arm_gicv3/gicd_no_migration_shift_bug",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = needed_always,
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.fields = (VMStateField[]) {
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VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_gicv3 = {
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.name = "arm_gicv3",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_load = gicv3_pre_load,
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.pre_save = gicv3_pre_save,
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.post_load = gicv3_post_load,
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.priority = MIG_PRI_GICV3,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(gicd_ctlr, GICv3State),
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VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
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VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE),
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VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ),
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VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ),
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VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State,
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DIV_ROUND_UP(GICV3_MAXIRQ, 16)),
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VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
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vmstate_gicv3_cpu, GICv3CPUState),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription * []) {
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&vmstate_gicv3_gicd_no_migration_shift_bug,
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NULL
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}
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};
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void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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const MemoryRegionOps *ops)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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int i;
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int cpuidx;
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/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
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* GPIO array layout is thus:
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* [0..N-1] spi
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* [N..N+31] PPIs for CPU 0
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* [N+32..N+63] PPIs for CPU 1
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* ...
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*/
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i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
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qdev_init_gpio_in(DEVICE(s), handler, i);
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
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}
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
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}
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->cpu[i].parent_virq);
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}
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for (i = 0; i < s->num_cpu; i++) {
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sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
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}
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memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
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"gicv3_dist", 0x10000);
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sysbus_init_mmio(sbd, &s->iomem_dist);
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s->redist_regions = g_new0(GICv3RedistRegion, s->nb_redist_regions);
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cpuidx = 0;
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for (i = 0; i < s->nb_redist_regions; i++) {
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char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
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GICv3RedistRegion *region = &s->redist_regions[i];
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region->gic = s;
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region->cpuidx = cpuidx;
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cpuidx += s->redist_region_count[i];
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memory_region_init_io(®ion->iomem, OBJECT(s),
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ops ? &ops[1] : NULL, region, name,
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s->redist_region_count[i] * GICV3_REDIST_SIZE);
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sysbus_init_mmio(sbd, ®ion->iomem);
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g_free(name);
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}
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}
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static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
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{
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GICv3State *s = ARM_GICV3_COMMON(dev);
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int i, rdist_capacity, cpuidx;
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/* revision property is actually reserved and currently used only in order
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* to keep the interface compatible with GICv2 code, avoiding extra
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* conditions. However, in future it could be used, for example, if we
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* implement GICv4.
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*/
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if (s->revision != 3) {
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error_setg(errp, "unsupported GIC revision %d", s->revision);
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return;
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}
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if (s->num_irq > GICV3_MAXIRQ) {
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error_setg(errp,
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"requested %u interrupt lines exceeds GIC maximum %d",
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s->num_irq, GICV3_MAXIRQ);
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return;
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}
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if (s->num_irq < GIC_INTERNAL) {
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error_setg(errp,
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"requested %u interrupt lines is below GIC minimum %d",
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s->num_irq, GIC_INTERNAL);
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return;
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}
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if (s->num_cpu == 0) {
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error_setg(errp, "num-cpu must be at least 1");
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return;
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}
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/* ITLinesNumber is represented as (N / 32) - 1, so this is an
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* implementation imposed restriction, not an architectural one,
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* so we don't have to deal with bitfields where only some of the
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* bits in a 32-bit word should be valid.
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*/
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if (s->num_irq % 32) {
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error_setg(errp,
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"%d interrupt lines unsupported: not divisible by 32",
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s->num_irq);
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return;
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}
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if (s->lpi_enable && !s->dma) {
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error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
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return;
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}
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rdist_capacity = 0;
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for (i = 0; i < s->nb_redist_regions; i++) {
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rdist_capacity += s->redist_region_count[i];
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}
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if (rdist_capacity != s->num_cpu) {
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error_setg(errp, "Capacity of the redist regions(%d) "
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"does not match the number of vcpus(%d)",
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rdist_capacity, s->num_cpu);
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return;
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}
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if (s->lpi_enable) {
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address_space_init(&s->dma_as, s->dma,
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"gicv3-its-sysmem");
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}
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s->cpu = g_new0(GICv3CPUState, s->num_cpu);
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for (i = 0; i < s->num_cpu; i++) {
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CPUState *cpu = qemu_get_cpu(i);
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uint64_t cpu_affid;
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s->cpu[i].cpu = cpu;
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s->cpu[i].gic = s;
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/* Store GICv3CPUState in CPUARMState gicv3state pointer */
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gicv3_set_gicv3state(cpu, &s->cpu[i]);
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/* Pre-construct the GICR_TYPER:
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* For our implementation:
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* Top 32 bits are the affinity value of the associated CPU
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* CommonLPIAff == 01 (redistributors with same Aff3 share LPI table)
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* Processor_Number == CPU index starting from 0
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* DPGS == 0 (GICR_CTLR.DPG* not supported)
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* Last == 1 if this is the last redistributor in a series of
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* contiguous redistributor pages
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* DirectLPI == 0 (direct injection of LPIs not supported)
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* VLPIS == 0 (virtual LPIs not supported)
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* PLPIS == 0 (physical LPIs not supported)
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*/
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cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL);
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/* The CPU mp-affinity property is in MPIDR register format; squash
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* the affinity bytes into 32 bits as the GICR_TYPER has them.
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*/
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cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) |
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(cpu_affid & 0xFFFFFF);
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s->cpu[i].gicr_typer = (cpu_affid << 32) |
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(1 << 24) |
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(i << 8);
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if (s->lpi_enable) {
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s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
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}
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}
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/*
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* Now go through and set GICR_TYPER.Last for the final
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* redistributor in each region.
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*/
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cpuidx = 0;
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for (i = 0; i < s->nb_redist_regions; i++) {
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cpuidx += s->redist_region_count[i];
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s->cpu[cpuidx - 1].gicr_typer |= GICR_TYPER_LAST;
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}
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}
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static void arm_gicv3_finalize(Object *obj)
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{
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GICv3State *s = ARM_GICV3_COMMON(obj);
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g_free(s->redist_region_count);
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}
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static void arm_gicv3_common_reset(DeviceState *dev)
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{
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GICv3State *s = ARM_GICV3_COMMON(dev);
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int i;
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for (i = 0; i < s->num_cpu; i++) {
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GICv3CPUState *cs = &s->cpu[i];
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cs->level = 0;
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cs->gicr_ctlr = 0;
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if (s->lpi_enable) {
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/* Our implementation supports clearing GICR_CTLR.EnableLPIs */
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cs->gicr_ctlr |= GICR_CTLR_CES;
|
|
}
|
|
cs->gicr_statusr[GICV3_S] = 0;
|
|
cs->gicr_statusr[GICV3_NS] = 0;
|
|
cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
|
|
cs->gicr_propbaser = 0;
|
|
cs->gicr_pendbaser = 0;
|
|
/* If we're resetting a TZ-aware GIC as if secure firmware
|
|
* had set it up ready to start a kernel in non-secure, we
|
|
* need to set interrupts to group 1 so the kernel can use them.
|
|
* Otherwise they reset to group 0 like the hardware.
|
|
*/
|
|
if (s->irq_reset_nonsecure) {
|
|
cs->gicr_igroupr0 = 0xffffffff;
|
|
} else {
|
|
cs->gicr_igroupr0 = 0;
|
|
}
|
|
|
|
cs->gicr_ienabler0 = 0;
|
|
cs->gicr_ipendr0 = 0;
|
|
cs->gicr_iactiver0 = 0;
|
|
cs->edge_trigger = 0xffff;
|
|
cs->gicr_igrpmodr0 = 0;
|
|
cs->gicr_nsacr = 0;
|
|
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
|
|
|
|
cs->hppi.prio = 0xff;
|
|
cs->hpplpi.prio = 0xff;
|
|
|
|
/* State in the CPU interface must *not* be reset here, because it
|
|
* is part of the CPU's reset domain, not the GIC device's.
|
|
*/
|
|
}
|
|
|
|
/* For our implementation affinity routing is always enabled */
|
|
if (s->security_extn) {
|
|
s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS;
|
|
} else {
|
|
s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE;
|
|
}
|
|
|
|
s->gicd_statusr[GICV3_S] = 0;
|
|
s->gicd_statusr[GICV3_NS] = 0;
|
|
|
|
memset(s->group, 0, sizeof(s->group));
|
|
memset(s->grpmod, 0, sizeof(s->grpmod));
|
|
memset(s->enabled, 0, sizeof(s->enabled));
|
|
memset(s->pending, 0, sizeof(s->pending));
|
|
memset(s->active, 0, sizeof(s->active));
|
|
memset(s->level, 0, sizeof(s->level));
|
|
memset(s->edge_trigger, 0, sizeof(s->edge_trigger));
|
|
memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority));
|
|
memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter));
|
|
memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr));
|
|
/* GICD_IROUTER are UNKNOWN at reset so in theory the guest must
|
|
* write these to get sane behaviour and we need not populate the
|
|
* pointer cache here; however having the cache be different for
|
|
* "happened to be 0 from reset" and "guest wrote 0" would be
|
|
* too confusing.
|
|
*/
|
|
gicv3_cache_all_target_cpustates(s);
|
|
|
|
if (s->irq_reset_nonsecure) {
|
|
/* If we're resetting a TZ-aware GIC as if secure firmware
|
|
* had set it up ready to start a kernel in non-secure, we
|
|
* need to set interrupts to group 1 so the kernel can use them.
|
|
* Otherwise they reset to group 0 like the hardware.
|
|
*/
|
|
for (i = GIC_INTERNAL; i < s->num_irq; i++) {
|
|
gicv3_gicd_group_set(s, i);
|
|
}
|
|
}
|
|
s->gicd_no_migration_shift_bug = true;
|
|
}
|
|
|
|
static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
|
|
bool secure_boot)
|
|
{
|
|
GICv3State *s = ARM_GICV3_COMMON(obj);
|
|
|
|
if (s->security_extn && !secure_boot) {
|
|
/* We're directly booting a kernel into NonSecure. If this GIC
|
|
* implements the security extensions then we must configure it
|
|
* to have all the interrupts be NonSecure (this is a job that
|
|
* is done by the Secure boot firmware in real hardware, and in
|
|
* this mode QEMU is acting as a minimalist firmware-and-bootloader
|
|
* equivalent).
|
|
*/
|
|
s->irq_reset_nonsecure = true;
|
|
}
|
|
}
|
|
|
|
static Property arm_gicv3_common_properties[] = {
|
|
DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
|
|
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
|
|
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
|
|
DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
|
|
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
|
|
DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
|
|
redist_region_count, qdev_prop_uint32, uint32_t),
|
|
DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
|
|
MemoryRegion *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
|
|
|
|
dc->reset = arm_gicv3_common_reset;
|
|
dc->realize = arm_gicv3_common_realize;
|
|
device_class_set_props(dc, arm_gicv3_common_properties);
|
|
dc->vmsd = &vmstate_gicv3;
|
|
albifc->arm_linux_init = arm_gic_common_linux_init;
|
|
}
|
|
|
|
static const TypeInfo arm_gicv3_common_type = {
|
|
.name = TYPE_ARM_GICV3_COMMON,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(GICv3State),
|
|
.class_size = sizeof(ARMGICv3CommonClass),
|
|
.class_init = arm_gicv3_common_class_init,
|
|
.instance_finalize = arm_gicv3_finalize,
|
|
.abstract = true,
|
|
.interfaces = (InterfaceInfo []) {
|
|
{ TYPE_ARM_LINUX_BOOT_IF },
|
|
{ },
|
|
},
|
|
};
|
|
|
|
static void register_types(void)
|
|
{
|
|
type_register_static(&arm_gicv3_common_type);
|
|
}
|
|
|
|
type_init(register_types)
|