389 lines
17 KiB
Plaintext
389 lines
17 KiB
Plaintext
CPUs perform independent memory operations effectively in random order.
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but this can be a problem for CPU-CPU interaction (including interactions
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between QEMU and the guest). Multi-threaded programs use various tools
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to instruct the compiler and the CPU to restrict the order to something
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that is consistent with the expectations of the programmer.
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The most basic tool is locking. Mutexes, condition variables and
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semaphores are used in QEMU, and should be the default approach to
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synchronization. Anything else is considerably harder, but it's
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also justified more often than one would like. The two tools that
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are provided by qemu/atomic.h are memory barriers and atomic operations.
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Macros defined by qemu/atomic.h fall in three camps:
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- compiler barriers: barrier();
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- weak atomic access and manual memory barriers: atomic_read(),
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atomic_set(), smp_rmb(), smp_wmb(), smp_mb(), smp_mb_acquire(),
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smp_mb_release(), smp_read_barrier_depends();
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- sequentially consistent atomic access: everything else.
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COMPILER MEMORY BARRIER
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=======================
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barrier() prevents the compiler from moving the memory accesses either
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side of it to the other side. The compiler barrier has no direct effect
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on the CPU, which may then reorder things however it wishes.
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barrier() is mostly used within qemu/atomic.h itself. On some
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architectures, CPU guarantees are strong enough that blocking compiler
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optimizations already ensures the correct order of execution. In this
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case, qemu/atomic.h will reduce stronger memory barriers to simple
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compiler barriers.
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Still, barrier() can be useful when writing code that can be interrupted
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by signal handlers.
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SEQUENTIALLY CONSISTENT ATOMIC ACCESS
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=====================================
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Most of the operations in the qemu/atomic.h header ensure *sequential
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consistency*, where "the result of any execution is the same as if the
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operations of all the processors were executed in some sequential order,
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and the operations of each individual processor appear in this sequence
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in the order specified by its program".
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qemu/atomic.h provides the following set of atomic read-modify-write
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operations:
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void atomic_inc(ptr)
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void atomic_dec(ptr)
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void atomic_add(ptr, val)
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void atomic_sub(ptr, val)
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void atomic_and(ptr, val)
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void atomic_or(ptr, val)
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typeof(*ptr) atomic_fetch_inc(ptr)
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typeof(*ptr) atomic_fetch_dec(ptr)
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typeof(*ptr) atomic_fetch_add(ptr, val)
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typeof(*ptr) atomic_fetch_sub(ptr, val)
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typeof(*ptr) atomic_fetch_and(ptr, val)
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typeof(*ptr) atomic_fetch_or(ptr, val)
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typeof(*ptr) atomic_xchg(ptr, val)
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typeof(*ptr) atomic_cmpxchg(ptr, old, new)
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all of which return the old value of *ptr. These operations are
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polymorphic; they operate on any type that is as wide as an int.
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Sequentially consistent loads and stores can be done using:
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atomic_fetch_add(ptr, 0) for loads
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atomic_xchg(ptr, val) for stores
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However, they are quite expensive on some platforms, notably POWER and
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ARM. Therefore, qemu/atomic.h provides two primitives with slightly
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weaker constraints:
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typeof(*ptr) atomic_mb_read(ptr)
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void atomic_mb_set(ptr, val)
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The semantics of these primitives map to Java volatile variables,
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and are strongly related to memory barriers as used in the Linux
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kernel (see below).
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As long as you use atomic_mb_read and atomic_mb_set, accesses cannot
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be reordered with each other, and it is also not possible to reorder
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"normal" accesses around them.
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However, and this is the important difference between
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atomic_mb_read/atomic_mb_set and sequential consistency, it is important
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for both threads to access the same volatile variable. It is not the
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case that everything visible to thread A when it writes volatile field f
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becomes visible to thread B after it reads volatile field g. The store
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and load have to "match" (i.e., be performed on the same volatile
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field) to achieve the right semantics.
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These operations operate on any type that is as wide as an int or smaller.
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WEAK ATOMIC ACCESS AND MANUAL MEMORY BARRIERS
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=============================================
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Compared to sequentially consistent atomic access, programming with
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weaker consistency models can be considerably more complicated.
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In general, if the algorithm you are writing includes both writes
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and reads on the same side, it is generally simpler to use sequentially
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consistent primitives.
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When using this model, variables are accessed with atomic_read() and
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atomic_set(), and restrictions to the ordering of accesses is enforced
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using the memory barrier macros: smp_rmb(), smp_wmb(), smp_mb(),
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smp_mb_acquire(), smp_mb_release(), smp_read_barrier_depends().
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atomic_read() and atomic_set() prevents the compiler from using
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optimizations that might otherwise optimize accesses out of existence
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on the one hand, or that might create unsolicited accesses on the other.
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In general this should not have any effect, because the same compiler
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barriers are already implied by memory barriers. However, it is useful
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to do so, because it tells readers which variables are shared with
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other threads, and which are local to the current thread or protected
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by other, more mundane means.
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Memory barriers control the order of references to shared memory.
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They come in six kinds:
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- smp_rmb() guarantees that all the LOAD operations specified before
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the barrier will appear to happen before all the LOAD operations
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specified after the barrier with respect to the other components of
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the system.
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In other words, smp_rmb() puts a partial ordering on loads, but is not
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required to have any effect on stores.
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- smp_wmb() guarantees that all the STORE operations specified before
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the barrier will appear to happen before all the STORE operations
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specified after the barrier with respect to the other components of
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the system.
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In other words, smp_wmb() puts a partial ordering on stores, but is not
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required to have any effect on loads.
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- smp_mb_acquire() guarantees that all the LOAD operations specified before
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the barrier will appear to happen before all the LOAD or STORE operations
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specified after the barrier with respect to the other components of
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the system.
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- smp_mb_release() guarantees that all the STORE operations specified *after*
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the barrier will appear to happen after all the LOAD or STORE operations
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specified *before* the barrier with respect to the other components of
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the system.
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- smp_mb() guarantees that all the LOAD and STORE operations specified
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before the barrier will appear to happen before all the LOAD and
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STORE operations specified after the barrier with respect to the other
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components of the system.
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smp_mb() puts a partial ordering on both loads and stores. It is
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stronger than both a read and a write memory barrier; it implies both
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smp_mb_acquire() and smp_mb_release(), but it also prevents STOREs
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coming before the barrier from overtaking LOADs coming after the
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barrier and vice versa.
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- smp_read_barrier_depends() is a weaker kind of read barrier. On
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most processors, whenever two loads are performed such that the
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second depends on the result of the first (e.g., the first load
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retrieves the address to which the second load will be directed),
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the processor will guarantee that the first LOAD will appear to happen
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before the second with respect to the other components of the system.
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However, this is not always true---for example, it was not true on
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Alpha processors. Whenever this kind of access happens to shared
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memory (that is not protected by a lock), a read barrier is needed,
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and smp_read_barrier_depends() can be used instead of smp_rmb().
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Note that the first load really has to have a _data_ dependency and not
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a control dependency. If the address for the second load is dependent
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on the first load, but the dependency is through a conditional rather
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than actually loading the address itself, then it's a _control_
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dependency and a full read barrier or better is required.
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This is the set of barriers that is required *between* two atomic_read()
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and atomic_set() operations to achieve sequential consistency:
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| 2nd operation |
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|-----------------------------------------------|
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1st operation | (after last) | atomic_read | atomic_set |
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---------------+----------------+-------------+----------------|
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(before first) | | none | smp_mb_release |
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---------------+----------------+-------------+----------------|
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atomic_read | smp_mb_acquire | smp_rmb | ** |
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---------------+----------------+-------------+----------------|
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atomic_set | none | smp_mb()*** | smp_wmb() |
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---------------+----------------+-------------+----------------|
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* Or smp_read_barrier_depends().
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** This requires a load-store barrier. This is achieved by
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either smp_mb_acquire() or smp_mb_release().
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*** This requires a store-load barrier. On most machines, the only
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way to achieve this is a full barrier.
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You can see that the two possible definitions of atomic_mb_read()
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and atomic_mb_set() are the following:
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1) atomic_mb_read(p) = atomic_read(p); smp_mb_acquire()
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atomic_mb_set(p, v) = smp_mb_release(); atomic_set(p, v); smp_mb()
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2) atomic_mb_read(p) = smp_mb() atomic_read(p); smp_mb_acquire()
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atomic_mb_set(p, v) = smp_mb_release(); atomic_set(p, v);
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Usually the former is used, because smp_mb() is expensive and a program
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normally has more reads than writes. Therefore it makes more sense to
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make atomic_mb_set() the more expensive operation.
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There are two common cases in which atomic_mb_read and atomic_mb_set
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generate too many memory barriers, and thus it can be useful to manually
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place barriers instead:
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- when a data structure has one thread that is always a writer
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and one thread that is always a reader, manual placement of
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memory barriers makes the write side faster. Furthermore,
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correctness is easy to check for in this case using the "pairing"
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trick that is explained below:
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thread 1 thread 1
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------------------------- ------------------------
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(other writes)
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smp_mb_release()
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atomic_mb_set(&a, x) atomic_set(&a, x)
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smp_wmb()
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atomic_mb_set(&b, y) atomic_set(&b, y)
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=>
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thread 2 thread 2
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------------------------- ------------------------
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y = atomic_mb_read(&b) y = atomic_read(&b)
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smp_rmb()
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x = atomic_mb_read(&a) x = atomic_read(&a)
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smp_mb_acquire()
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Note that the barrier between the stores in thread 1, and between
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the loads in thread 2, has been optimized here to a write or a
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read memory barrier respectively. On some architectures, notably
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ARMv7, smp_mb_acquire and smp_mb_release are just as expensive as
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smp_mb, but smp_rmb and/or smp_wmb are more efficient.
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- sometimes, a thread is accessing many variables that are otherwise
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unrelated to each other (for example because, apart from the current
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thread, exactly one other thread will read or write each of these
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variables). In this case, it is possible to "hoist" the implicit
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barriers provided by atomic_mb_read() and atomic_mb_set() outside
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a loop. For example, the above definition atomic_mb_read() gives
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the following transformation:
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n = 0; n = 0;
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for (i = 0; i < 10; i++) => for (i = 0; i < 10; i++)
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n += atomic_mb_read(&a[i]); n += atomic_read(&a[i]);
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smp_mb_acquire();
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Similarly, atomic_mb_set() can be transformed as follows:
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smp_mb():
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smp_mb_release();
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for (i = 0; i < 10; i++) => for (i = 0; i < 10; i++)
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atomic_mb_set(&a[i], false); atomic_set(&a[i], false);
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smp_mb();
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The two tricks can be combined. In this case, splitting a loop in
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two lets you hoist the barriers out of the loops _and_ eliminate the
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expensive smp_mb():
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smp_mb_release();
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for (i = 0; i < 10; i++) { => for (i = 0; i < 10; i++)
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atomic_mb_set(&a[i], false); atomic_set(&a[i], false);
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atomic_mb_set(&b[i], false); smb_wmb();
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} for (i = 0; i < 10; i++)
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atomic_set(&a[i], false);
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smp_mb();
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The other thread can still use atomic_mb_read()/atomic_mb_set()
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Memory barrier pairing
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----------------------
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A useful rule of thumb is that memory barriers should always, or almost
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always, be paired with another barrier. In the case of QEMU, however,
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note that the other barrier may actually be in a driver that runs in
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the guest!
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For the purposes of pairing, smp_read_barrier_depends() and smp_rmb()
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both count as read barriers. A read barrier shall pair with a write
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barrier or a full barrier; a write barrier shall pair with a read
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barrier or a full barrier. A full barrier can pair with anything.
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For example:
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thread 1 thread 2
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=============== ===============
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a = 1;
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smp_wmb();
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b = 2; x = b;
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smp_rmb();
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y = a;
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Note that the "writing" thread is accessing the variables in the
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opposite order as the "reading" thread. This is expected: stores
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before the write barrier will normally match the loads after the
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read barrier, and vice versa. The same is true for more than 2
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access and for data dependency barriers:
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thread 1 thread 2
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=============== ===============
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b[2] = 1;
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smp_wmb();
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x->i = 2;
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smp_wmb();
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a = x; x = a;
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smp_read_barrier_depends();
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y = x->i;
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smp_read_barrier_depends();
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z = b[y];
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smp_wmb() also pairs with atomic_mb_read() and smp_mb_acquire().
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and smp_rmb() also pairs with atomic_mb_set() and smp_mb_release().
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COMPARISON WITH LINUX KERNEL MEMORY BARRIERS
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============================================
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Here is a list of differences between Linux kernel atomic operations
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and memory barriers, and the equivalents in QEMU:
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- atomic operations in Linux are always on a 32-bit int type and
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use a boxed atomic_t type; atomic operations in QEMU are polymorphic
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and use normal C types.
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- Originally, atomic_read and atomic_set in Linux gave no guarantee
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at all. Linux 4.1 updated them to implement volatile
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semantics via ACCESS_ONCE (or the more recent READ/WRITE_ONCE).
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QEMU's atomic_read/set implement, if the compiler supports it, C11
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atomic relaxed semantics, and volatile semantics otherwise.
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Both semantics prevent the compiler from doing certain transformations;
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the difference is that atomic accesses are guaranteed to be atomic,
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while volatile accesses aren't. Thus, in the volatile case we just cross
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our fingers hoping that the compiler will generate atomic accesses,
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since we assume the variables passed are machine-word sized and
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properly aligned.
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No barriers are implied by atomic_read/set in either Linux or QEMU.
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- atomic read-modify-write operations in Linux are of three kinds:
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atomic_OP returns void
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atomic_OP_return returns new value of the variable
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atomic_fetch_OP returns the old value of the variable
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atomic_cmpxchg returns the old value of the variable
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In QEMU, the second kind does not exist. Currently Linux has
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atomic_fetch_or only. QEMU provides and, or, inc, dec, add, sub.
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- different atomic read-modify-write operations in Linux imply
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a different set of memory barriers; in QEMU, all of them enforce
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sequential consistency, which means they imply full memory barriers
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before and after the operation.
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- Linux does not have an equivalent of atomic_mb_set(). In particular,
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note that smp_store_mb() is a little weaker than atomic_mb_set().
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atomic_mb_read() compiles to the same instructions as Linux's
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smp_load_acquire(), but this should be treated as an implementation
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detail. QEMU does have atomic_load_acquire() and atomic_store_release()
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macros, but for now they are only used within atomic.h. This may
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change in the future.
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SOURCES
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=======
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* Documentation/memory-barriers.txt from the Linux kernel
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* "The JSR-133 Cookbook for Compiler Writers", available at
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http://g.oswego.edu/dl/jmm/cookbook.html
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