304 lines
9.2 KiB
C
304 lines
9.2 KiB
C
/*
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* Microblaze MMU emulation for qemu.
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*
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* Copyright (c) 2009 Edgar E. Iglesias
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#define D(x)
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static unsigned int tlb_decode_size(unsigned int f)
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{
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static const unsigned int sizes[] = {
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1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
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1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
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};
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assert(f < ARRAY_SIZE(sizes));
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return sizes[f];
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}
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static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
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{
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CPUState *cs = CPU(mb_env_get_cpu(env));
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struct microblaze_mmu *mmu = &env->mmu;
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unsigned int tlb_size;
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uint32_t tlb_tag, end, t;
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t = mmu->rams[RAM_TAG][idx];
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if (!(t & TLB_VALID))
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return;
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tlb_tag = t & TLB_EPN_MASK;
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tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
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end = tlb_tag + tlb_size;
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while (tlb_tag < end) {
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tlb_flush_page(cs, tlb_tag);
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tlb_tag += TARGET_PAGE_SIZE;
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}
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}
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static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
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{
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struct microblaze_mmu *mmu = &env->mmu;
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unsigned int i;
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uint32_t t;
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if (newpid & ~0xff)
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qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);
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for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
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/* Lookup and decode. */
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t = mmu->rams[RAM_TAG][i];
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if (t & TLB_VALID) {
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if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
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mmu_flush_idx(env, i);
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}
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}
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}
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/* rw - 0 = read, 1 = write, 2 = fetch. */
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unsigned int mmu_translate(struct microblaze_mmu *mmu,
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struct microblaze_mmu_lookup *lu,
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target_ulong vaddr, int rw, int mmu_idx)
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{
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unsigned int i, hit = 0;
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unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
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unsigned int tlb_size;
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uint32_t tlb_tag, tlb_rpn, mask, t0;
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lu->err = ERR_MISS;
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for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
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uint32_t t, d;
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/* Lookup and decode. */
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t = mmu->rams[RAM_TAG][i];
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D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
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if (t & TLB_VALID) {
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tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
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if (tlb_size < TARGET_PAGE_SIZE) {
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qemu_log("%d pages not supported\n", tlb_size);
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abort();
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}
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mask = ~(tlb_size - 1);
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tlb_tag = t & TLB_EPN_MASK;
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if ((vaddr & mask) != (tlb_tag & mask)) {
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D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
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i, vaddr & mask, tlb_tag & mask));
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continue;
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}
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if (mmu->tids[i]
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&& ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
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D(qemu_log("TLB %d pid=%x != tid=%x\n",
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i, mmu->regs[MMU_R_PID], mmu->tids[i]));
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continue;
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}
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/* Bring in the data part. */
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d = mmu->rams[RAM_DATA][i];
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tlb_ex = d & TLB_EX;
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tlb_wr = d & TLB_WR;
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/* Now let's see if there is a zone that overrides the protbits. */
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tlb_zsel = (d >> 4) & 0xf;
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t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
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t0 &= 0x3;
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if (tlb_zsel > mmu->c_mmu_zones) {
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qemu_log_mask(LOG_GUEST_ERROR, "tlb zone select out of range! %d\n", tlb_zsel);
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t0 = 1; /* Ignore. */
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}
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if (mmu->c_mmu == 1) {
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t0 = 1; /* Zones are disabled. */
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}
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switch (t0) {
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case 0:
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if (mmu_idx == MMU_USER_IDX)
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continue;
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break;
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case 2:
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if (mmu_idx != MMU_USER_IDX) {
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tlb_ex = 1;
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tlb_wr = 1;
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}
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break;
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case 3:
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tlb_ex = 1;
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tlb_wr = 1;
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break;
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default: break;
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}
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lu->err = ERR_PROT;
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lu->prot = PAGE_READ;
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if (tlb_wr)
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lu->prot |= PAGE_WRITE;
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else if (rw == 1)
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goto done;
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if (tlb_ex)
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lu->prot |=PAGE_EXEC;
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else if (rw == 2) {
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goto done;
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}
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tlb_rpn = d & TLB_RPN_MASK;
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lu->vaddr = tlb_tag;
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lu->paddr = tlb_rpn;
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lu->size = tlb_size;
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lu->err = ERR_HIT;
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lu->idx = i;
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hit = 1;
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goto done;
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}
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}
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done:
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D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
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vaddr, rw, tlb_wr, tlb_ex, hit));
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return hit;
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}
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/* Writes/reads to the MMU's special regs end up here. */
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uint32_t mmu_read(CPUMBState *env, uint32_t rn)
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{
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unsigned int i;
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uint32_t r;
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if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
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qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
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return 0;
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}
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switch (rn) {
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/* Reads to HI/LO trig reads from the mmu rams. */
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case MMU_R_TLBLO:
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case MMU_R_TLBHI:
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if (!(env->mmu.c_mmu_tlb_access & 1)) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return 0;
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}
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i = env->mmu.regs[MMU_R_TLBX] & 0xff;
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r = env->mmu.rams[rn & 1][i];
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if (rn == MMU_R_TLBHI)
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env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
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break;
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case MMU_R_PID:
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case MMU_R_ZPR:
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if (!(env->mmu.c_mmu_tlb_access & 1)) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return 0;
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}
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r = env->mmu.regs[rn];
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break;
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default:
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r = env->mmu.regs[rn];
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break;
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}
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D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
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return r;
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}
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void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
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{
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MicroBlazeCPU *cpu = mb_env_get_cpu(env);
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unsigned int i;
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D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
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if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
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qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
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return;
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}
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switch (rn) {
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/* Writes to HI/LO trig writes to the mmu rams. */
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case MMU_R_TLBLO:
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case MMU_R_TLBHI:
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i = env->mmu.regs[MMU_R_TLBX] & 0xff;
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if (rn == MMU_R_TLBHI) {
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if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
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qemu_log_mask(LOG_GUEST_ERROR, "invalidating index %x at pc=%x\n",
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i, env->sregs[SR_PC]);
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env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
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mmu_flush_idx(env, i);
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}
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env->mmu.rams[rn & 1][i] = v;
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D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v));
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break;
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case MMU_R_ZPR:
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if (env->mmu.c_mmu_tlb_access <= 1) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return;
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}
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/* Changes to the zone protection reg flush the QEMU TLB.
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Fortunately, these are very uncommon. */
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if (v != env->mmu.regs[rn]) {
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tlb_flush(CPU(cpu), 1);
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}
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env->mmu.regs[rn] = v;
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break;
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case MMU_R_PID:
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if (env->mmu.c_mmu_tlb_access <= 1) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return;
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}
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if (v != env->mmu.regs[rn]) {
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mmu_change_pid(env, v);
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env->mmu.regs[rn] = v;
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}
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break;
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case MMU_R_TLBSX:
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{
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struct microblaze_mmu_lookup lu;
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int hit;
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if (env->mmu.c_mmu_tlb_access <= 1) {
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid access to MMU reg %d\n", rn);
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return;
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}
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hit = mmu_translate(&env->mmu, &lu,
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v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
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if (hit) {
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env->mmu.regs[MMU_R_TLBX] = lu.idx;
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} else
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env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
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break;
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}
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default:
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env->mmu.regs[rn] = v;
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break;
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}
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}
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void mmu_init(struct microblaze_mmu *mmu)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
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mmu->regs[i] = 0;
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}
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}
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