845 lines
26 KiB
C
845 lines
26 KiB
C
/*
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* QEMU Sun4u/Sun4v System Emulator
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci-host/sabre.h"
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#include "hw/char/serial.h"
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#include "hw/char/parallel.h"
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#include "hw/timer/m48t59.h"
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#include "hw/input/i8042.h"
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#include "hw/block/fdc.h"
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#include "net/net.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "hw/nvram/sun_nvram.h"
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#include "hw/nvram/chrp_nvram.h"
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#include "hw/sparc/sparc64.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/sysbus.h"
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#include "hw/ide.h"
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#include "hw/ide/pci.h"
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#include "hw/loader.h"
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#include "hw/fw-path-provider.h"
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#include "elf.h"
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#include "trace.h"
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#define KERNEL_LOAD_ADDR 0x00404000
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#define CMDLINE_ADDR 0x003ff000
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#define PROM_SIZE_MAX (4 * MiB)
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#define PROM_VADDR 0x000ffd00000ULL
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#define PBM_SPECIAL_BASE 0x1fe00000000ULL
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#define PBM_MEM_BASE 0x1ff00000000ULL
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#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
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#define PROM_FILENAME "openbios-sparc64"
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#define NVRAM_SIZE 0x2000
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#define MAX_IDE_BUS 2
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#define BIOS_CFG_IOPORT 0x510
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#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
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#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
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#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
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#define IVEC_MAX 0x40
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struct hwdef {
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uint16_t machine_id;
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uint64_t prom_addr;
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uint64_t console_serial_base;
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};
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typedef struct EbusState {
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/*< private >*/
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PCIDevice parent_obj;
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ISABus *isa_bus;
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qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
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uint64_t console_serial_base;
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MemoryRegion bar0;
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MemoryRegion bar1;
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} EbusState;
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#define TYPE_EBUS "ebus"
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#define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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{
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
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const char *arch, ram_addr_t RAM_size,
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const char *boot_devices,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth,
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const uint8_t *macaddr)
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{
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unsigned int i;
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int sysp_end;
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uint8_t image[0x1ff0];
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NvramClass *k = NVRAM_GET_CLASS(nvram);
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memset(image, '\0', sizeof(image));
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/* OpenBIOS nvram variables partition */
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sysp_end = chrp_nvram_create_system_partition(image, 0);
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/* Free space partition */
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chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
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for (i = 0; i < sizeof(image); i++) {
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(k->write)(nvram, i, image[i]);
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}
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return 0;
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}
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static uint64_t sun4u_load_kernel(const char *kernel_filename,
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const char *initrd_filename,
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ram_addr_t RAM_size, uint64_t *initrd_size,
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uint64_t *initrd_addr, uint64_t *kernel_addr,
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uint64_t *kernel_entry)
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{
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int linux_boot;
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unsigned int i;
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long kernel_size;
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uint8_t *ptr;
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uint64_t kernel_top = 0;
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
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kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
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if (kernel_size < 0) {
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*kernel_addr = KERNEL_LOAD_ADDR;
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*kernel_entry = KERNEL_LOAD_ADDR;
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
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RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
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TARGET_PAGE_SIZE);
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}
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if (kernel_size < 0) {
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kernel_size = load_image_targphys(kernel_filename,
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KERNEL_LOAD_ADDR,
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RAM_size - KERNEL_LOAD_ADDR);
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}
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if (kernel_size < 0) {
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error_report("could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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/* load initrd above kernel */
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*initrd_size = 0;
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if (initrd_filename && kernel_top) {
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*initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
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*initrd_size = load_image_targphys(initrd_filename,
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*initrd_addr,
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RAM_size - *initrd_addr);
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if ((int)*initrd_size < 0) {
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error_report("could not load initial ram disk '%s'",
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initrd_filename);
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exit(1);
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}
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}
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if (*initrd_size > 0) {
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
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ptr = rom_ptr(*kernel_addr + i, 32);
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if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
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stl_p(ptr + 24, *initrd_addr + *kernel_addr);
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stl_p(ptr + 28, *initrd_size);
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break;
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}
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}
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}
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}
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return kernel_size;
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}
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typedef struct ResetData {
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SPARCCPU *cpu;
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uint64_t prom_addr;
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} ResetData;
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#define TYPE_SUN4U_POWER "power"
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#define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER)
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typedef struct PowerDevice {
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SysBusDevice parent_obj;
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MemoryRegion power_mmio;
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} PowerDevice;
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/* Power */
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static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
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{
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return 0;
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}
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static void power_mem_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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/* According to a real Ultra 5, bit 24 controls the power */
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if (val & 0x1000000) {
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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}
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}
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static const MemoryRegionOps power_mem_ops = {
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.read = power_mem_read,
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.write = power_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void power_realize(DeviceState *dev, Error **errp)
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{
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PowerDevice *d = SUN4U_POWER(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
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"power", sizeof(uint32_t));
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sysbus_init_mmio(sbd, &d->power_mmio);
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}
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static void power_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = power_realize;
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}
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static const TypeInfo power_info = {
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.name = TYPE_SUN4U_POWER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PowerDevice),
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.class_init = power_class_init,
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};
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static void ebus_isa_irq_handler(void *opaque, int n, int level)
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{
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EbusState *s = EBUS(opaque);
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qemu_irq irq = s->isa_bus_irqs[n];
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/* Pass ISA bus IRQs onto their gpio equivalent */
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trace_ebus_isa_irq_handler(n, level);
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if (irq) {
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qemu_set_irq(irq, level);
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}
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}
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/* EBUS (Eight bit bus) bridge */
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static void ebus_realize(PCIDevice *pci_dev, Error **errp)
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{
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EbusState *s = EBUS(pci_dev);
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SysBusDevice *sbd;
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DeviceState *dev;
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qemu_irq *isa_irq;
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DriveInfo *fd[MAX_FD];
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int i;
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s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
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pci_address_space_io(pci_dev), errp);
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if (!s->isa_bus) {
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error_setg(errp, "unable to instantiate EBUS ISA bus");
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return;
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}
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/* ISA bus */
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isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
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isa_bus_irqs(s->isa_bus, isa_irq);
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qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
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ISA_NUM_IRQS);
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/* Serial ports */
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i = 0;
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if (s->console_serial_base) {
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serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
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0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
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i++;
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}
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serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
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/* Parallel ports */
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parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
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/* Keyboard */
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isa_create_simple(s->isa_bus, "i8042");
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/* Floppy */
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for (i = 0; i < MAX_FD; i++) {
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fd[i] = drive_get(IF_FLOPPY, 0, i);
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}
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dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
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if (fd[0]) {
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qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
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&error_abort);
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}
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if (fd[1]) {
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qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
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&error_abort);
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}
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qdev_prop_set_uint32(dev, "dma", -1);
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qdev_init_nofail(dev);
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/* Power */
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dev = qdev_create(NULL, TYPE_SUN4U_POWER);
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qdev_init_nofail(dev);
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sbd = SYS_BUS_DEVICE(dev);
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memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
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sysbus_mmio_get_region(sbd, 0));
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/* PCI */
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pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
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pci_dev->config[0x05] = 0x00;
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pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
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pci_dev->config[0x07] = 0x03; // status = medium devsel
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pci_dev->config[0x09] = 0x00; // programming i/f
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pci_dev->config[0x0D] = 0x0a; // latency_timer
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memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
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0, 0x1000000);
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pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
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memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
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0, 0x8000);
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pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
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}
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static Property ebus_properties[] = {
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DEFINE_PROP_UINT64("console-serial-base", EbusState,
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console_serial_base, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void ebus_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = ebus_realize;
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k->vendor_id = PCI_VENDOR_ID_SUN;
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k->device_id = PCI_DEVICE_ID_SUN_EBUS;
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k->revision = 0x01;
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k->class_id = PCI_CLASS_BRIDGE_OTHER;
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dc->props = ebus_properties;
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}
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static const TypeInfo ebus_info = {
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.name = TYPE_EBUS,
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.parent = TYPE_PCI_DEVICE,
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.class_init = ebus_class_init,
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.instance_size = sizeof(EbusState),
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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#define TYPE_OPENPROM "openprom"
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#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
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typedef struct PROMState {
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SysBusDevice parent_obj;
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MemoryRegion prom;
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} PROMState;
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static uint64_t translate_prom_address(void *opaque, uint64_t addr)
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{
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hwaddr *base_addr = (hwaddr *)opaque;
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return addr + *base_addr - PROM_VADDR;
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}
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/* Boot PROM (OpenBIOS) */
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static void prom_init(hwaddr addr, const char *bios_name)
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{
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DeviceState *dev;
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SysBusDevice *s;
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char *filename;
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int ret;
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dev = qdev_create(NULL, TYPE_OPENPROM);
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(s, 0, addr);
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/* load boot prom */
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if (bios_name == NULL) {
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bios_name = PROM_FILENAME;
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}
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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if (filename) {
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ret = load_elf(filename, NULL, translate_prom_address, &addr,
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NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
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if (ret < 0 || ret > PROM_SIZE_MAX) {
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ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
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}
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g_free(filename);
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} else {
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ret = -1;
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}
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if (ret < 0 || ret > PROM_SIZE_MAX) {
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error_report("could not load prom '%s'", bios_name);
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exit(1);
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}
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}
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static void prom_realize(DeviceState *ds, Error **errp)
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{
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PROMState *s = OPENPROM(ds);
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SysBusDevice *dev = SYS_BUS_DEVICE(ds);
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Error *local_err = NULL;
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memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
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PROM_SIZE_MAX, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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vmstate_register_ram_global(&s->prom);
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memory_region_set_readonly(&s->prom, true);
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sysbus_init_mmio(dev, &s->prom);
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}
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static Property prom_properties[] = {
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{/* end of property list */},
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};
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static void prom_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = prom_properties;
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dc->realize = prom_realize;
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}
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static const TypeInfo prom_info = {
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.name = TYPE_OPENPROM,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PROMState),
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.class_init = prom_class_init,
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};
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#define TYPE_SUN4U_MEMORY "memory"
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#define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
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typedef struct RamDevice {
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SysBusDevice parent_obj;
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MemoryRegion ram;
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uint64_t size;
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} RamDevice;
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|
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/* System RAM */
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static void ram_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
RamDevice *d = SUN4U_RAM(dev);
|
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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|
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memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
|
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&error_fatal);
|
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vmstate_register_ram_global(&d->ram);
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sysbus_init_mmio(sbd, &d->ram);
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}
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|
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static void ram_init(hwaddr addr, ram_addr_t RAM_size)
|
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{
|
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DeviceState *dev;
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SysBusDevice *s;
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RamDevice *d;
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|
|
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/* allocate RAM */
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dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
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s = SYS_BUS_DEVICE(dev);
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d = SUN4U_RAM(dev);
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d->size = RAM_size;
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qdev_init_nofail(dev);
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sysbus_mmio_map(s, 0, addr);
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}
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|
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static Property ram_properties[] = {
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DEFINE_PROP_UINT64("size", RamDevice, size, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void ram_class_init(ObjectClass *klass, void *data)
|
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{
|
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DeviceClass *dc = DEVICE_CLASS(klass);
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|
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dc->realize = ram_realize;
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dc->props = ram_properties;
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}
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static const TypeInfo ram_info = {
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.name = TYPE_SUN4U_MEMORY,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(RamDevice),
|
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.class_init = ram_class_init,
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};
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|
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static void sun4uv_init(MemoryRegion *address_space_mem,
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MachineState *machine,
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const struct hwdef *hwdef)
|
|
{
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SPARCCPU *cpu;
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Nvram *nvram;
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unsigned int i;
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uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
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SabreState *sabre;
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PCIBus *pci_bus, *pci_busA, *pci_busB;
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PCIDevice *ebus, *pci_dev;
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SysBusDevice *s;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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DeviceState *iommu, *dev;
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FWCfgState *fw_cfg;
|
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NICInfo *nd;
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MACAddr macaddr;
|
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bool onboard_nic;
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|
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/* init CPUs */
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cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
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|
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/* IOMMU */
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iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
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qdev_init_nofail(iommu);
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|
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/* set up devices */
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ram_init(0, machine->ram_size);
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prom_init(hwdef->prom_addr, bios_name);
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/* Init sabre (PCI host bridge) */
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sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
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qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
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qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
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object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
|
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&error_abort);
|
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qdev_init_nofail(DEVICE(sabre));
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|
|
|
/* Wire up PCI interrupts to CPU */
|
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for (i = 0; i < IVEC_MAX; i++) {
|
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qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
|
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qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
|
|
}
|
|
|
|
pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
|
|
pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
|
|
pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
|
|
|
|
/* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
|
|
reserved (leaving no slots free after on-board devices) however slots
|
|
0-3 are free on busB */
|
|
pci_bus->slot_reserved_mask = 0xfffffffc;
|
|
pci_busA->slot_reserved_mask = 0xfffffff1;
|
|
pci_busB->slot_reserved_mask = 0xfffffff0;
|
|
|
|
ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
|
|
qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
|
|
hwdef->console_serial_base);
|
|
qdev_init_nofail(DEVICE(ebus));
|
|
|
|
/* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
|
|
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
|
|
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
|
|
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
|
|
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
|
|
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
|
|
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
|
|
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
|
|
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
|
|
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
|
|
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
|
|
|
|
switch (vga_interface_type) {
|
|
case VGA_STD:
|
|
pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
|
|
break;
|
|
case VGA_NONE:
|
|
break;
|
|
default:
|
|
abort(); /* Should not happen - types are checked in vl.c already */
|
|
}
|
|
|
|
memset(&macaddr, 0, sizeof(MACAddr));
|
|
onboard_nic = false;
|
|
for (i = 0; i < nb_nics; i++) {
|
|
nd = &nd_table[i];
|
|
|
|
if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
|
|
if (!onboard_nic) {
|
|
pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
|
|
true, "sunhme");
|
|
memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
|
|
onboard_nic = true;
|
|
} else {
|
|
pci_dev = pci_create(pci_busB, -1, "sunhme");
|
|
}
|
|
} else {
|
|
pci_dev = pci_create(pci_busB, -1, nd->model);
|
|
}
|
|
|
|
dev = &pci_dev->qdev;
|
|
qdev_set_nic_properties(dev, nd);
|
|
qdev_init_nofail(dev);
|
|
}
|
|
|
|
/* If we don't have an onboard NIC, grab a default MAC address so that
|
|
* we have a valid machine id */
|
|
if (!onboard_nic) {
|
|
qemu_macaddr_default_if_unset(&macaddr);
|
|
}
|
|
|
|
ide_drive_get(hd, ARRAY_SIZE(hd));
|
|
|
|
pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
|
|
qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
|
|
qdev_init_nofail(&pci_dev->qdev);
|
|
pci_ide_create_devs(pci_dev, hd);
|
|
|
|
/* Map NVRAM into I/O (ebus) space */
|
|
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
|
|
s = SYS_BUS_DEVICE(nvram);
|
|
memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
|
|
sysbus_mmio_get_region(s, 0));
|
|
|
|
initrd_size = 0;
|
|
initrd_addr = 0;
|
|
kernel_size = sun4u_load_kernel(machine->kernel_filename,
|
|
machine->initrd_filename,
|
|
ram_size, &initrd_size, &initrd_addr,
|
|
&kernel_addr, &kernel_entry);
|
|
|
|
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
|
|
machine->boot_order,
|
|
kernel_addr, kernel_size,
|
|
machine->kernel_cmdline,
|
|
initrd_addr, initrd_size,
|
|
/* XXX: need an option to load a NVRAM image */
|
|
0,
|
|
graphic_width, graphic_height, graphic_depth,
|
|
(uint8_t *)&macaddr);
|
|
|
|
dev = qdev_create(NULL, TYPE_FW_CFG_IO);
|
|
qdev_prop_set_bit(dev, "dma_enabled", false);
|
|
object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
|
|
qdev_init_nofail(dev);
|
|
memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
|
|
&FW_CFG_IO(dev)->comb_iomem);
|
|
|
|
fw_cfg = FW_CFG(dev);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
|
if (machine->kernel_cmdline) {
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
|
|
strlen(machine->kernel_cmdline) + 1);
|
|
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
|
|
} else {
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
|
}
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
|
|
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
|
}
|
|
|
|
enum {
|
|
sun4u_id = 0,
|
|
sun4v_id = 64,
|
|
};
|
|
|
|
/*
|
|
* Implementation of an interface to adjust firmware path
|
|
* for the bootindex property handling.
|
|
*/
|
|
static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
|
|
DeviceState *dev)
|
|
{
|
|
PCIDevice *pci;
|
|
IDEBus *ide_bus;
|
|
IDEState *ide_s;
|
|
int bus_id;
|
|
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
|
|
pci = PCI_DEVICE(dev);
|
|
|
|
if (PCI_FUNC(pci->devfn)) {
|
|
return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
|
|
PCI_FUNC(pci->devfn));
|
|
} else {
|
|
return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
|
|
}
|
|
}
|
|
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
|
|
ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
|
|
ide_s = idebus_active_if(ide_bus);
|
|
bus_id = ide_bus->bus_id;
|
|
|
|
if (ide_s->drive_kind == IDE_CD) {
|
|
return g_strdup_printf("ide@%x/cdrom", bus_id);
|
|
}
|
|
|
|
return g_strdup_printf("ide@%x/disk", bus_id);
|
|
}
|
|
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
|
|
return g_strdup("disk");
|
|
}
|
|
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
|
|
return g_strdup("cdrom");
|
|
}
|
|
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
|
|
return g_strdup("disk");
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static const struct hwdef hwdefs[] = {
|
|
/* Sun4u generic PC-like machine */
|
|
{
|
|
.machine_id = sun4u_id,
|
|
.prom_addr = 0x1fff0000000ULL,
|
|
.console_serial_base = 0,
|
|
},
|
|
/* Sun4v generic PC-like machine */
|
|
{
|
|
.machine_id = sun4v_id,
|
|
.prom_addr = 0x1fff0000000ULL,
|
|
.console_serial_base = 0,
|
|
},
|
|
};
|
|
|
|
/* Sun4u hardware initialisation */
|
|
static void sun4u_init(MachineState *machine)
|
|
{
|
|
sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
|
|
}
|
|
|
|
/* Sun4v hardware initialisation */
|
|
static void sun4v_init(MachineState *machine)
|
|
{
|
|
sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
|
|
}
|
|
|
|
static void sun4u_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
|
|
|
|
mc->desc = "Sun4u platform";
|
|
mc->init = sun4u_init;
|
|
mc->block_default_type = IF_IDE;
|
|
mc->max_cpus = 1; /* XXX for now */
|
|
mc->is_default = 1;
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
|
|
mc->ignore_boot_device_suffixes = true;
|
|
mc->default_display = "std";
|
|
fwc->get_dev_path = sun4u_fw_dev_path;
|
|
}
|
|
|
|
static const TypeInfo sun4u_type = {
|
|
.name = MACHINE_TYPE_NAME("sun4u"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = sun4u_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_FW_PATH_PROVIDER },
|
|
{ }
|
|
},
|
|
};
|
|
|
|
static void sun4v_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "Sun4v platform";
|
|
mc->init = sun4v_init;
|
|
mc->block_default_type = IF_IDE;
|
|
mc->max_cpus = 1; /* XXX for now */
|
|
mc->default_boot_order = "c";
|
|
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
|
|
mc->default_display = "std";
|
|
}
|
|
|
|
static const TypeInfo sun4v_type = {
|
|
.name = MACHINE_TYPE_NAME("sun4v"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = sun4v_class_init,
|
|
};
|
|
|
|
static void sun4u_register_types(void)
|
|
{
|
|
type_register_static(&power_info);
|
|
type_register_static(&ebus_info);
|
|
type_register_static(&prom_info);
|
|
type_register_static(&ram_info);
|
|
|
|
type_register_static(&sun4u_type);
|
|
type_register_static(&sun4v_type);
|
|
}
|
|
|
|
type_init(sun4u_register_types)
|