Cédric Le Goater c4e1f0b483 aspeed/smc: Add support for DMAs ... The FMC controller on the Aspeed SoCs support DMA to access the flash modules. It can operate in a normal mode, to copy to or from the flash module mapping window, or in a checksum calculation mode, to evaluate the best clock settings for reads. The model introduces two custom address spaces for DMAs: one for the AHB window of the FMC flash devices and one for the DRAM. The latter is populated using a "dram" link set from the machine with the RAM container region. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Joel Stanley <joel@jms.id.au> Message-id: 20190904070506.1052-6-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2019-09-13 16:05:01 +01:00
..
aspeed_smc.h	aspeed/smc: Add support for DMAs	2019-09-13 16:05:01 +01:00
imx_spi.h
mss-spi.h
pl022.h
ssi.h	Include hw/qdev-properties.h less	2019-08-16 13:31:53 +02:00
stm32f2xx_spi.h	Include hw/hw.h exactly where needed	2019-08-16 13:31:52 +02:00
xilinx_spips.h	include: Make headers more self-contained	2019-08-16 13:31:51 +02:00