d5938f29fe
In my "build everything" tree, changing sysemu/sysemu.h triggers a recompile of some 5400 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). Almost a third of its inclusions are actually superfluous. Delete them. Downgrade two more to qapi/qapi-types-run-state.h, and move one from char/serial.h to char/serial.c. hw/semihosting/config.c, monitor/monitor.c, qdev-monitor.c, and stubs/semihost.c define variables declared in sysemu/sysemu.h without including it. The compiler is cool with that, but include it anyway. This doesn't reduce actual use much, as it's still included into widely included headers. The next commit will tackle that. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-27-armbru@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
89 lines
1.9 KiB
C
89 lines
1.9 KiB
C
/*
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* QEMU HP-PARISC PCI support functions.
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*
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*/
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#include "qemu/osdep.h"
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#include "hppa_sys.h"
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#include "qemu/log.h"
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#include "trace.h"
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/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */
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static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size)
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{
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return 0;
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}
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static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size)
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{
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}
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const MemoryRegionOps hppa_pci_ignore_ops = {
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.read = ignore_read,
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.write = ignore_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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/* PCI config space reads/writes, to byte-word addressable memory. */
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static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PCIBus *b = opaque;
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return pci_data_read(b, addr, size);
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}
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static void bw_conf1_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIBus *b = opaque;
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pci_data_write(b, addr, val, size);
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}
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const MemoryRegionOps hppa_pci_conf1_ops = {
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.read = bw_conf1_read,
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.write = bw_conf1_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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/* PCI/EISA Interrupt Acknowledge Cycle. */
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static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
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{
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return pic_read_irq(isa_pic);
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}
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static void special_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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trace_hppa_pci_iack_write();
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}
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const MemoryRegionOps hppa_pci_iack_ops = {
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.read = iack_read,
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.write = special_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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