d4d7a59a7a
The existing implementation remains same and ics-base is introduced. The
type name "ics" is retained, and all the related functions renamed as
ics_simple_*
This will allow different implementations for the source controllers
such as the MSI support of PHB3 on Power8 which uses in-memory state
tables for example.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[ clg: added ICS_BASE_GET_CLASS and related fixes, based on :
http://patchwork.ozlabs.org/patch/646010/ ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
209 lines
6.6 KiB
C
209 lines
6.6 KiB
C
/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#ifndef XICS_H
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#define XICS_H
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#include "hw/sysbus.h"
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#define TYPE_XICS_COMMON "xics-common"
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#define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON)
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/*
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* Retain xics as the type name to be compatible for migration. Rest all the
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* functions, class and variables are renamed as xics_spapr.
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*/
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#define TYPE_XICS_SPAPR "xics"
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#define XICS_SPAPR(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_SPAPR)
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#define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
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#define XICS_SPAPR_KVM(obj) \
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OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
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#define XICS_COMMON_CLASS(klass) \
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OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
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#define XICS_SPAPR_CLASS(klass) \
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OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_SPAPR)
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#define XICS_COMMON_GET_CLASS(obj) \
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OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
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#define XICS_SPAPR_GET_CLASS(obj) \
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OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR)
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#define XICS_IPI 0x2
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#define XICS_BUID 0x1
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#define XICS_IRQ_BASE (XICS_BUID << 12)
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/*
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* We currently only support one BUID which is our interrupt base
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* (the kernel implementation supports more but we don't exploit
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* that yet)
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*/
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typedef struct XICSStateClass XICSStateClass;
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typedef struct XICSState XICSState;
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typedef struct ICPStateClass ICPStateClass;
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typedef struct ICPState ICPState;
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typedef struct ICSStateClass ICSStateClass;
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typedef struct ICSState ICSState;
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typedef struct ICSIRQState ICSIRQState;
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struct XICSStateClass {
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DeviceClass parent_class;
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void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu);
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void (*set_nr_irqs)(XICSState *icp, uint32_t nr_irqs, Error **errp);
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void (*set_nr_servers)(XICSState *icp, uint32_t nr_servers, Error **errp);
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};
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struct XICSState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t nr_servers;
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uint32_t nr_irqs;
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ICPState *ss;
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QLIST_HEAD(, ICSState) ics;
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};
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#define TYPE_ICP "icp"
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#define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
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#define TYPE_KVM_ICP "icp-kvm"
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#define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
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#define ICP_CLASS(klass) \
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OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
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#define ICP_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
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struct ICPStateClass {
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DeviceClass parent_class;
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void (*pre_save)(ICPState *s);
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int (*post_load)(ICPState *s, int version_id);
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};
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struct ICPState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CPUState *cs;
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ICSState *xirr_owner;
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uint32_t xirr;
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uint8_t pending_priority;
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uint8_t mfrr;
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qemu_irq output;
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bool cap_irq_xics_enabled;
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};
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#define TYPE_ICS_BASE "ics-base"
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#define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE)
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/* Retain ics for sPAPR for migration from existing sPAPR guests */
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#define TYPE_ICS_SIMPLE "ics"
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#define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
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#define TYPE_ICS_KVM "icskvm"
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#define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM)
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#define ICS_BASE_CLASS(klass) \
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OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE)
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#define ICS_BASE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE)
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struct ICSStateClass {
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DeviceClass parent_class;
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void (*pre_save)(ICSState *s);
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int (*post_load)(ICSState *s, int version_id);
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void (*reject)(ICSState *s, uint32_t irq);
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void (*resend)(ICSState *s);
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void (*eoi)(ICSState *s, uint32_t irq);
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};
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struct ICSState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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uint32_t nr_irqs;
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uint32_t offset;
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qemu_irq *qirqs;
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ICSIRQState *irqs;
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XICSState *xics;
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QLIST_ENTRY(ICSState) list;
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};
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static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
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{
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return (ics->offset != 0) && (nr >= ics->offset)
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&& (nr < (ics->offset + ics->nr_irqs));
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}
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struct ICSIRQState {
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uint32_t server;
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uint8_t priority;
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uint8_t saved_priority;
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#define XICS_STATUS_ASSERTED 0x1
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#define XICS_STATUS_SENT 0x2
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#define XICS_STATUS_REJECTED 0x4
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#define XICS_STATUS_MASKED_PENDING 0x8
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uint8_t status;
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/* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
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#define XICS_FLAGS_IRQ_LSI 0x1
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#define XICS_FLAGS_IRQ_MSI 0x2
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#define XICS_FLAGS_IRQ_MASK 0x3
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uint8_t flags;
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};
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#define XICS_IRQS_SPAPR 1024
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qemu_irq xics_get_qirq(XICSState *icp, int irq);
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int xics_spapr_alloc(XICSState *icp, int irq_hint, bool lsi, Error **errp);
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int xics_spapr_alloc_block(XICSState *icp, int num, bool lsi, bool align,
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Error **errp);
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void xics_spapr_free(XICSState *icp, int irq, int num);
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void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
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void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
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/* Internal XICS interfaces */
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int xics_get_cpu_index_by_dt_id(int cpu_dt_id);
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void icp_set_cppr(XICSState *icp, int server, uint8_t cppr);
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void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr);
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uint32_t icp_accept(ICPState *ss);
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uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
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void icp_eoi(XICSState *icp, int server, uint32_t xirr);
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void ics_simple_write_xive(ICSState *ics, int nr, int server,
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uint8_t priority, uint8_t saved_priority);
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void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
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ICSState *xics_find_source(XICSState *icp, int irq);
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#endif /* XICS_H */
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