Marc-André Lureau 0f9668e0c1 Remove qemu-common.h include from most units ... Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2022-04-06 14:31:55 +02:00
..
insn_trans	Replace config-time define HOST_WORDS_BIGENDIAN	2022-04-06 10:50:37 +02:00
arch_dump.c
bitmanip_helper.c
cpu_bits.h	target/riscv: add support for svpbmt extension	2022-02-16 12:25:52 +10:00
cpu_helper.c	target/riscv: hardwire mstatus.FS to zero when enable zfinx	2022-03-03 13:14:50 +10:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: expose zfinx, zdinx, zhinx{min} properties	2022-03-03 13:14:50 +10:00
cpu.h	Move CPU softfloat unions to cpu-float.h	2022-04-06 14:31:43 +02:00
csr.c	target/riscv: Avoid leaking "no translation" TLB entries	2022-04-01 08:40:42 +10:00
fpu_helper.c	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
gdbstub.c
helper.h	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
insn16.decode
insn32.decode	target/riscv: add support for svinval extension	2022-02-16 12:25:52 +10:00
instmap.h
internals.h	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c	Remove qemu-common.h include from most units	2022-04-06 14:31:55 +02:00
m128_helper.c
machine.c	target/riscv: Implement AIA xiselect and xireg CSRs	2022-02-16 12:24:19 +10:00
meson.build	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
monitor.c
op_helper.c
pmp.c
pmp.h	target: Include missing 'cpu.h'	2022-03-06 13:15:42 +01:00
sbi_ecall_interface.h
trace-events
trace.h
translate.c	target/riscv: add support for zdinx	2022-03-03 13:14:50 +10:00
vector_helper.c	Replace config-time define HOST_WORDS_BIGENDIAN	2022-04-06 10:50:37 +02:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00