qemu-e2k/include/hw/arm
Peter Delevoryas 5d63d0c76c hw/arm/aspeed: Allow machine to set UART default
When you run QEMU with an Aspeed machine and a single serial device
using stdio like this:

    qemu -machine ast2600-evb -drive ... -serial stdio

The guest OS can read and write to the UART5 registers at 0x1E784000 and
it will receive from stdin and write to stdout. The Aspeed SoC's have a
lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on
the board design, may be using any of them as the serial console. (See
"stdout-path" in a DTS to check which one is chosen).

Most boards, including all of those currently defined in
hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds
some flexibility for different boards without requiring users to change
their command-line invocation of QEMU.

I tested this doesn't break existing code by booting an AST2500 OpenBMC
image and an AST2600 OpenBMC image, each using UART5 as the console.

Then I tested switching the default to UART1 and booting an AST2600
OpenBMC image that uses UART1, and that worked too.

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210901153615.2746885-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-09-20 08:50:59 +02:00
..
allwinner-a10.h
allwinner-h3.h
armsse-version.h
armsse.h
armv7m.h hw/arm/armv7m: Create input clocks 2021-09-01 11:08:19 +01:00
aspeed_soc.h hw/arm/aspeed: Allow machine to set UART default 2021-09-20 08:50:59 +02:00
aspeed.h hw/arm/aspeed: Allow machine to set UART default 2021-09-20 08:50:59 +02:00
bcm2835_peripherals.h
bcm2836.h
boot.h
digic.h
exynos4210.h
fdt.h
fsl-imx6.h
fsl-imx6ul.h
fsl-imx7.h
fsl-imx25.h
fsl-imx31.h
linux-boot-if.h
msf2-soc.h hw/arm/msf2-soc: Wire up refclk 2021-09-01 11:08:20 +01:00
npcm7xx.h
nrf51_soc.h hw/arm/nrf51: Wire up sysclk 2021-09-01 11:08:20 +01:00
nrf51.h
omap.h
primecell.h
pxa.h
raspi_platform.h
sharpsl.h
smmu-common.h
smmuv3.h
soc_dma.h
stm32f100_soc.h hw/arm/stm32f100: Wire up sysclk and refclk 2021-09-01 11:08:19 +01:00
stm32f205_soc.h hw/arm/stm32f205: Wire up sysclk and refclk 2021-09-01 11:08:19 +01:00
stm32f405_soc.h hw/arm/stm32f405: Wire up sysclk and refclk 2021-09-01 11:08:19 +01:00
sysbus-fdt.h
virt.h hw/arm/virt: add ITS support in virt GIC 2021-09-13 21:01:08 +01:00
xlnx-versal.h
xlnx-zynqmp.h