qemu-e2k/target/riscv
Paolo Bonzini eccae02d99 meson: remove dead code
Found with "muon analyze".

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-09-01 07:42:37 +02:00
..
insn_trans
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: Update default priority table for local interrupts 2022-07-03 10:03:20 +10:00
cpu_helper.c target/riscv: Update default priority table for local interrupts 2022-07-03 10:03:20 +10:00
cpu_user.h
cpu-param.h
cpu.c RISC-V: Allow both Zmmul and M 2022-07-27 17:34:02 +10:00
cpu.h target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
crypto_helper.c
csr.c target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits 2022-07-03 10:03:20 +10:00
debug.c
debug.h
fpu_helper.c
gdbstub.c
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c
m128_helper.c
machine.c target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
meson.build meson: remove dead code 2022-09-01 07:42:37 +02:00
monitor.c
op_helper.c
pmp.c target/riscv/pmp: guard against PMP ranges with a negative size 2022-07-03 10:03:20 +10:00
pmp.h
pmu.c target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
pmu.h target/riscv: Support mcycle/minstret write operation 2022-07-03 10:03:20 +10:00
sbi_ecall_interface.h
trace-events
trace.h
translate.c
vector_helper.c
XVentanaCondOps.decode