c227f0995e
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Something
like this _must_ be presented on the list first so people can provide input
and cope with it.
This reverts commit 99a0949b72.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
268 lines
6.8 KiB
C
268 lines
6.8 KiB
C
/*
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* Microblaze helper routines.
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*
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* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <assert.h>
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#include "exec.h"
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#include "helper.h"
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#include "host-utils.h"
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#define D(x)
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#if !defined(CONFIG_USER_ONLY)
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#define MMUSUFFIX _mmu
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#define SHIFT 0
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#include "softmmu_template.h"
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#define SHIFT 1
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#include "softmmu_template.h"
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#define SHIFT 2
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#include "softmmu_template.h"
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#define SHIFT 3
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#include "softmmu_template.h"
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/* Try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
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{
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TranslationBlock *tb;
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CPUState *saved_env;
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unsigned long pc;
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int ret;
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env;
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env = cpu_single_env;
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ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
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if (unlikely(ret)) {
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if (retaddr) {
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/* now we have a real cpu fault */
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pc = (unsigned long)retaddr;
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tb = tb_find_pc(pc);
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, NULL);
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}
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}
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cpu_loop_exit();
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}
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env = saved_env;
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}
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#endif
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void helper_raise_exception(uint32_t index)
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{
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env->exception_index = index;
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cpu_loop_exit();
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}
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void helper_debug(void)
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{
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int i;
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qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
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for (i = 0; i < 32; i++) {
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qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
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if ((i + 1) % 4 == 0)
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qemu_log("\n");
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}
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qemu_log("\n\n");
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}
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static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
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{
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uint32_t cout = 0;
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if ((b == ~0) && cin)
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cout = 1;
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else if ((~0 - a) < (b + cin))
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cout = 1;
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return cout;
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}
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uint32_t helper_cmp(uint32_t a, uint32_t b)
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{
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uint32_t t;
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t = b + ~a + 1;
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if ((b & 0x80000000) ^ (a & 0x80000000))
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t = (t & 0x7fffffff) | (b & 0x80000000);
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return t;
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}
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uint32_t helper_cmpu(uint32_t a, uint32_t b)
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{
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uint32_t t;
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t = b + ~a + 1;
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if ((b & 0x80000000) ^ (a & 0x80000000))
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t = (t & 0x7fffffff) | (a & 0x80000000);
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return t;
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}
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uint32_t helper_addkc(uint32_t a, uint32_t b, uint32_t k, uint32_t c)
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{
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uint32_t d, cf = 0, ncf;
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if (c)
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cf = env->sregs[SR_MSR] >> 31;
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assert(cf == 0 || cf == 1);
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d = a + b + cf;
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if (!k) {
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ncf = compute_carry(a, b, cf);
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assert(ncf == 0 || ncf == 1);
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if (ncf)
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env->sregs[SR_MSR] |= MSR_C | MSR_CC;
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else
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env->sregs[SR_MSR] &= ~(MSR_C | MSR_CC);
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}
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D(qemu_log("%x = %x + %x cf=%d ncf=%d k=%d c=%d\n",
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d, a, b, cf, ncf, k, c));
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return d;
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}
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uint32_t helper_subkc(uint32_t a, uint32_t b, uint32_t k, uint32_t c)
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{
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uint32_t d, cf = 1, ncf;
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if (c)
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cf = env->sregs[SR_MSR] >> 31;
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assert(cf == 0 || cf == 1);
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d = b + ~a + cf;
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if (!k) {
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ncf = compute_carry(b, ~a, cf);
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assert(ncf == 0 || ncf == 1);
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if (ncf)
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env->sregs[SR_MSR] |= MSR_C | MSR_CC;
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else
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env->sregs[SR_MSR] &= ~(MSR_C | MSR_CC);
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}
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D(qemu_log("%x = %x + %x cf=%d ncf=%d k=%d c=%d\n",
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d, a, b, cf, ncf, k, c));
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return d;
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}
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static inline int div_prepare(uint32_t a, uint32_t b)
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{
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if (b == 0) {
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env->sregs[SR_MSR] |= MSR_DZ;
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if ((env->sregs[SR_MSR] & MSR_EE)
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&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
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env->sregs[SR_ESR] = ESR_EC_DIVZERO;
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helper_raise_exception(EXCP_HW_EXCP);
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}
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return 0;
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}
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env->sregs[SR_MSR] &= ~MSR_DZ;
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return 1;
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}
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uint32_t helper_divs(uint32_t a, uint32_t b)
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{
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if (!div_prepare(a, b))
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return 0;
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return (int32_t)a / (int32_t)b;
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}
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uint32_t helper_divu(uint32_t a, uint32_t b)
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{
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if (!div_prepare(a, b))
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return 0;
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return a / b;
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}
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uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
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{
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unsigned int i;
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uint32_t mask = 0xff000000;
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for (i = 0; i < 4; i++) {
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if ((a & mask) == (b & mask))
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return i + 1;
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mask >>= 8;
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}
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return 0;
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}
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void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
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{
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if (addr & mask) {
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qemu_log_mask(CPU_LOG_INT,
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"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
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addr, mask, wr, dr);
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env->sregs[SR_EAR] = addr;
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env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
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| (dr & 31) << 5;
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if (mask == 3) {
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env->sregs[SR_ESR] |= 1 << 11;
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}
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if (!(env->sregs[SR_MSR] & MSR_EE)) {
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return;
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}
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helper_raise_exception(EXCP_HW_EXCP);
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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/* Writes/reads to the MMU's special regs end up here. */
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uint32_t helper_mmu_read(uint32_t rn)
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{
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return mmu_read(env, rn);
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}
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void helper_mmu_write(uint32_t rn, uint32_t v)
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{
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mmu_write(env, rn, v);
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}
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#endif
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void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
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int is_asi, int size)
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{
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CPUState *saved_env;
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env;
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env = cpu_single_env;
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qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
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addr, is_write, is_exec);
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if (!(env->sregs[SR_MSR] & MSR_EE)) {
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return;
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}
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env->sregs[SR_EAR] = addr;
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if (is_exec) {
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if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
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env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
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helper_raise_exception(EXCP_HW_EXCP);
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}
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} else {
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if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
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env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
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helper_raise_exception(EXCP_HW_EXCP);
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}
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}
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}
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