Leon Alrae f93c3a8d0c target-mips: flush QEMU TLB when disabling 64-bit addressing ... CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit Kernel/Supervisor/User Segments. If bit is cleared an access to corresponding segment should generate Address Error Exception. However, the guest may still be able to access some pages belonging to the disabled 64-bit segment because we forget to flush QEMU TLB. This patch fixes it. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>		2015-11-24 11:01:03 +00:00
..
cpu-qom.h
cpu.c	target-mips: implement the CPU wake-up on non-enabled interrupts in R6	2015-10-29 16:16:44 +00:00
cpu.h	target-mips: flush QEMU TLB when disabling 64-bit addressing	2015-11-24 11:01:03 +00:00
dsp_helper.c
gdbstub.c
helper.c	target-mips: Fix exceptions while UX=0	2015-11-24 11:01:03 +00:00
helper.h	target-mips: add PC, XNP reg numbers to RDHWR	2015-10-30 14:35:52 +00:00
kvm_mips.h
kvm.c	kvm: Pass PCI device pointer to MSI routing functions	2015-10-19 10:13:07 +02:00
lmi_helper.c
machine.c
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c	target-mips: improve exception handling	2015-09-18 12:07:24 +01:00
op_helper.c	target-mips: flush QEMU TLB when disabling 64-bit addressing	2015-11-24 11:01:03 +00:00
TODO
translate_init.c	target-mips: Set Config5.XNP for R6 cores	2015-10-30 14:36:19 +00:00
translate.c	target-mips: add SIGRIE instruction	2015-10-30 14:36:19 +00:00