qemu-e2k/target/riscv
Richard Henderson 2f668fabbc target/riscv: Avoid tcg_const_*
All uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05 13:46:13 -08:00
..
insn_trans target/riscv: Avoid tcg_const_* 2023-03-05 13:46:13 -08:00
arch_dump.c dump: Replace opaque DumpState pointer with a typed one 2022-10-06 19:30:43 +04:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: Add csr support for svadu 2023-03-01 17:28:15 -08:00
cpu_helper.c Merge patch series "target/riscv: Add support for Svadu extension" 2023-03-01 17:30:34 -08:00
cpu_user.h
cpu_vendorid.h RISC-V: Add initial support for T-Head C906 2023-02-07 08:19:23 +10:00
cpu-param.h
cpu.c Fifth RISC-V PR for QEMU 8.0 2023-03-03 11:04:46 +00:00
cpu.h Merge patch series "target/riscv: Add support for Svadu extension" 2023-03-01 17:30:34 -08:00
crypto_helper.c
csr.c Merge patch series "RISCVCPUConfig related cleanups" 2023-03-01 17:49:29 -08:00
debug.c target/riscv: set tval for triggered watchpoints 2023-02-07 08:19:23 +10:00
debug.h target/riscv: Add itrigger support when icount is enabled 2023-01-06 10:42:55 +10:00
fpu_helper.c target/riscv: Remove helper_set_rod_rounding_mode 2023-01-20 10:14:14 +10:00
gdbstub.c target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml 2023-03-01 16:40:20 -08:00
helper.h RISC-V: Adding XTheadSync ISA extension 2023-02-07 08:19:23 +10:00
insn16.decode target/riscv: fix shifts shamt value for rv128c 2022-09-07 09:18:32 +02:00
insn32.decode target/riscv: Add support for Zicond extension 2023-03-01 17:07:59 -08:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: rvv: Add mask agnostic for vv instructions 2022-09-07 09:18:32 +02:00
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c target/riscv: fix SBI getchar handler for KVM 2023-02-07 08:19:23 +10:00
m128_helper.c
machine.c target/riscv/cpu: remove CPUArchState::features and friends 2023-03-01 13:47:16 -08:00
meson.build RISC-V: Adding XTheadCmo ISA extension 2023-02-07 08:19:23 +10:00
monitor.c target/riscv: remove RISCV_FEATURE_MMU 2023-03-01 13:47:15 -08:00
op_helper.c target/riscv: remove RISCV_FEATURE_PMP 2023-03-01 13:47:13 -08:00
pmp.c target/riscv: remove RISCV_FEATURE_MMU 2023-03-01 13:47:15 -08:00
pmp.h target/riscv: Fix PMP propagation for tlb 2023-01-06 10:42:55 +10:00
pmu.c hw/riscv: virt: Add PMU DT node to the device tree 2022-09-07 09:19:15 +02:00
pmu.h riscv: Clean up includes 2023-02-08 07:28:05 +01:00
sbi_ecall_interface.h
time_helper.c target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX 2023-02-07 08:19:23 +10:00
time_helper.h target/riscv: Add stimecmp support 2022-09-07 09:19:15 +02:00
trace-events
trace.h
translate.c target/riscv: Avoid tcg_const_* 2023-03-05 13:46:13 -08:00
vector_helper.c target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig 2023-03-01 18:09:45 -08:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode