d710b33751
- Add PCS Register check to npcm_gmac-test Change-Id: I34821beb5e0b1e89e2be576ab58eabe41545af12 Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-7-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
345 lines
12 KiB
C
345 lines
12 KiB
C
/*
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* QTests for Nuvoton NPCM7xx/8xx GMAC Modules.
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*
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* Copyright 2024 Google LLC
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* Authors:
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* Hao Wu <wuhaotsh@google.com>
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* Nabih Estefan <nabihestefan@google.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "libqos/libqos.h"
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/* Name of the GMAC Device */
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#define TYPE_NPCM_GMAC "npcm-gmac"
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/* Address of the PCS Module */
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#define PCS_BASE_ADDRESS 0xf0780000
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#define NPCM_PCS_IND_AC_BA 0x1fe
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typedef struct GMACModule {
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int irq;
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uint64_t base_addr;
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} GMACModule;
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typedef struct TestData {
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const GMACModule *module;
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} TestData;
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/* Values extracted from hw/arm/npcm8xx.c */
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static const GMACModule gmac_module_list[] = {
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{
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.irq = 14,
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.base_addr = 0xf0802000
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},
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{
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.irq = 15,
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.base_addr = 0xf0804000
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},
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{
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.irq = 16,
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.base_addr = 0xf0806000
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},
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{
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.irq = 17,
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.base_addr = 0xf0808000
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}
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};
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/* Returns the index of the GMAC module. */
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static int gmac_module_index(const GMACModule *mod)
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{
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ptrdiff_t diff = mod - gmac_module_list;
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g_assert_true(diff >= 0 && diff < ARRAY_SIZE(gmac_module_list));
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return diff;
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}
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/* 32-bit register indices. Taken from npcm_gmac.c */
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typedef enum NPCMRegister {
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/* DMA Registers */
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NPCM_DMA_BUS_MODE = 0x1000,
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NPCM_DMA_XMT_POLL_DEMAND = 0x1004,
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NPCM_DMA_RCV_POLL_DEMAND = 0x1008,
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NPCM_DMA_RCV_BASE_ADDR = 0x100c,
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NPCM_DMA_TX_BASE_ADDR = 0x1010,
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NPCM_DMA_STATUS = 0x1014,
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NPCM_DMA_CONTROL = 0x1018,
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NPCM_DMA_INTR_ENA = 0x101c,
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NPCM_DMA_MISSED_FRAME_CTR = 0x1020,
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NPCM_DMA_HOST_TX_DESC = 0x1048,
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NPCM_DMA_HOST_RX_DESC = 0x104c,
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NPCM_DMA_CUR_TX_BUF_ADDR = 0x1050,
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NPCM_DMA_CUR_RX_BUF_ADDR = 0x1054,
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NPCM_DMA_HW_FEATURE = 0x1058,
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/* GMAC Registers */
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NPCM_GMAC_MAC_CONFIG = 0x0,
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NPCM_GMAC_FRAME_FILTER = 0x4,
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NPCM_GMAC_HASH_HIGH = 0x8,
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NPCM_GMAC_HASH_LOW = 0xc,
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NPCM_GMAC_MII_ADDR = 0x10,
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NPCM_GMAC_MII_DATA = 0x14,
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NPCM_GMAC_FLOW_CTRL = 0x18,
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NPCM_GMAC_VLAN_FLAG = 0x1c,
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NPCM_GMAC_VERSION = 0x20,
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NPCM_GMAC_WAKEUP_FILTER = 0x28,
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NPCM_GMAC_PMT = 0x2c,
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NPCM_GMAC_LPI_CTRL = 0x30,
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NPCM_GMAC_TIMER_CTRL = 0x34,
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NPCM_GMAC_INT_STATUS = 0x38,
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NPCM_GMAC_INT_MASK = 0x3c,
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NPCM_GMAC_MAC0_ADDR_HI = 0x40,
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NPCM_GMAC_MAC0_ADDR_LO = 0x44,
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NPCM_GMAC_MAC1_ADDR_HI = 0x48,
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NPCM_GMAC_MAC1_ADDR_LO = 0x4c,
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NPCM_GMAC_MAC2_ADDR_HI = 0x50,
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NPCM_GMAC_MAC2_ADDR_LO = 0x54,
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NPCM_GMAC_MAC3_ADDR_HI = 0x58,
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NPCM_GMAC_MAC3_ADDR_LO = 0x5c,
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NPCM_GMAC_RGMII_STATUS = 0xd8,
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NPCM_GMAC_WATCHDOG = 0xdc,
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NPCM_GMAC_PTP_TCR = 0x700,
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NPCM_GMAC_PTP_SSIR = 0x704,
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NPCM_GMAC_PTP_STSR = 0x708,
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NPCM_GMAC_PTP_STNSR = 0x70c,
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NPCM_GMAC_PTP_STSUR = 0x710,
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NPCM_GMAC_PTP_STNSUR = 0x714,
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NPCM_GMAC_PTP_TAR = 0x718,
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NPCM_GMAC_PTP_TTSR = 0x71c,
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/* PCS Registers */
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NPCM_PCS_SR_CTL_ID1 = 0x3c0008,
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NPCM_PCS_SR_CTL_ID2 = 0x3c000a,
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NPCM_PCS_SR_CTL_STS = 0x3c0010,
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NPCM_PCS_SR_MII_CTRL = 0x3e0000,
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NPCM_PCS_SR_MII_STS = 0x3e0002,
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NPCM_PCS_SR_MII_DEV_ID1 = 0x3e0004,
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NPCM_PCS_SR_MII_DEV_ID2 = 0x3e0006,
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NPCM_PCS_SR_MII_AN_ADV = 0x3e0008,
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NPCM_PCS_SR_MII_LP_BABL = 0x3e000a,
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NPCM_PCS_SR_MII_AN_EXPN = 0x3e000c,
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NPCM_PCS_SR_MII_EXT_STS = 0x3e001e,
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NPCM_PCS_SR_TIM_SYNC_ABL = 0x3e0e10,
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NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR = 0x3e0e12,
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NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR = 0x3e0e14,
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NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR = 0x3e0e16,
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NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR = 0x3e0e18,
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NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR = 0x3e0e1a,
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NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR = 0x3e0e1c,
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NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR = 0x3e0e1e,
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NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR = 0x3e0e20,
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NPCM_PCS_VR_MII_MMD_DIG_CTRL1 = 0x3f0000,
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NPCM_PCS_VR_MII_AN_CTRL = 0x3f0002,
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NPCM_PCS_VR_MII_AN_INTR_STS = 0x3f0004,
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NPCM_PCS_VR_MII_TC = 0x3f0006,
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NPCM_PCS_VR_MII_DBG_CTRL = 0x3f000a,
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NPCM_PCS_VR_MII_EEE_MCTRL0 = 0x3f000c,
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NPCM_PCS_VR_MII_EEE_TXTIMER = 0x3f0010,
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NPCM_PCS_VR_MII_EEE_RXTIMER = 0x3f0012,
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NPCM_PCS_VR_MII_LINK_TIMER_CTRL = 0x3f0014,
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NPCM_PCS_VR_MII_EEE_MCTRL1 = 0x3f0016,
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NPCM_PCS_VR_MII_DIG_STS = 0x3f0020,
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NPCM_PCS_VR_MII_ICG_ERRCNT1 = 0x3f0022,
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NPCM_PCS_VR_MII_MISC_STS = 0x3f0030,
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NPCM_PCS_VR_MII_RX_LSTS = 0x3f0040,
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NPCM_PCS_VR_MII_MP_TX_BSTCTRL0 = 0x3f0070,
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NPCM_PCS_VR_MII_MP_TX_LVLCTRL0 = 0x3f0074,
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NPCM_PCS_VR_MII_MP_TX_GENCTRL0 = 0x3f007a,
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NPCM_PCS_VR_MII_MP_TX_GENCTRL1 = 0x3f007c,
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NPCM_PCS_VR_MII_MP_TX_STS = 0x3f0090,
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NPCM_PCS_VR_MII_MP_RX_GENCTRL0 = 0x3f00b0,
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NPCM_PCS_VR_MII_MP_RX_GENCTRL1 = 0x3f00b2,
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NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0 = 0x3f00ba,
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NPCM_PCS_VR_MII_MP_MPLL_CTRL0 = 0x3f00f0,
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NPCM_PCS_VR_MII_MP_MPLL_CTRL1 = 0x3f00f2,
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NPCM_PCS_VR_MII_MP_MPLL_STS = 0x3f0110,
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NPCM_PCS_VR_MII_MP_MISC_CTRL2 = 0x3f0126,
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NPCM_PCS_VR_MII_MP_LVL_CTRL = 0x3f0130,
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NPCM_PCS_VR_MII_MP_MISC_CTRL0 = 0x3f0132,
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NPCM_PCS_VR_MII_MP_MISC_CTRL1 = 0x3f0134,
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NPCM_PCS_VR_MII_DIG_CTRL2 = 0x3f01c2,
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NPCM_PCS_VR_MII_DIG_ERRCNT_SEL = 0x3f01c4,
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} NPCMRegister;
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static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
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NPCMRegister regno)
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{
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return qtest_readl(qts, mod->base_addr + regno);
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}
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static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
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NPCMRegister regno)
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{
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uint32_t write_value = (regno & 0x3ffe00) >> 9;
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qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
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uint32_t read_offset = regno & 0x1ff;
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return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
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}
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/* Check that GMAC registers are reset to default value */
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static void test_init(gconstpointer test_data)
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{
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const TestData *td = test_data;
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const GMACModule *mod = td->module;
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QTestState *qts = qtest_init("-machine npcm845-evb");
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#define CHECK_REG32(regno, value) \
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do { \
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g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
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} while (0)
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#define CHECK_REG_PCS(regno, value) \
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do { \
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g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
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} while (0)
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CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
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CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
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CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
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CHECK_REG32(NPCM_DMA_RCV_BASE_ADDR, 0);
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CHECK_REG32(NPCM_DMA_TX_BASE_ADDR, 0);
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CHECK_REG32(NPCM_DMA_STATUS, 0);
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CHECK_REG32(NPCM_DMA_CONTROL, 0);
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CHECK_REG32(NPCM_DMA_INTR_ENA, 0);
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CHECK_REG32(NPCM_DMA_MISSED_FRAME_CTR, 0);
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CHECK_REG32(NPCM_DMA_HOST_TX_DESC, 0);
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CHECK_REG32(NPCM_DMA_HOST_RX_DESC, 0);
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CHECK_REG32(NPCM_DMA_CUR_TX_BUF_ADDR, 0);
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CHECK_REG32(NPCM_DMA_CUR_RX_BUF_ADDR, 0);
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CHECK_REG32(NPCM_DMA_HW_FEATURE, 0x100d4f37);
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CHECK_REG32(NPCM_GMAC_MAC_CONFIG, 0);
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CHECK_REG32(NPCM_GMAC_FRAME_FILTER, 0);
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CHECK_REG32(NPCM_GMAC_HASH_HIGH, 0);
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CHECK_REG32(NPCM_GMAC_HASH_LOW, 0);
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CHECK_REG32(NPCM_GMAC_MII_ADDR, 0);
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CHECK_REG32(NPCM_GMAC_MII_DATA, 0);
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CHECK_REG32(NPCM_GMAC_FLOW_CTRL, 0);
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CHECK_REG32(NPCM_GMAC_VLAN_FLAG, 0);
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CHECK_REG32(NPCM_GMAC_VERSION, 0x00001032);
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CHECK_REG32(NPCM_GMAC_WAKEUP_FILTER, 0);
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CHECK_REG32(NPCM_GMAC_PMT, 0);
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CHECK_REG32(NPCM_GMAC_LPI_CTRL, 0);
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CHECK_REG32(NPCM_GMAC_TIMER_CTRL, 0x03e80000);
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CHECK_REG32(NPCM_GMAC_INT_STATUS, 0);
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CHECK_REG32(NPCM_GMAC_INT_MASK, 0);
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CHECK_REG32(NPCM_GMAC_MAC0_ADDR_HI, 0x8000ffff);
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CHECK_REG32(NPCM_GMAC_MAC0_ADDR_LO, 0xffffffff);
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CHECK_REG32(NPCM_GMAC_MAC1_ADDR_HI, 0x0000ffff);
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CHECK_REG32(NPCM_GMAC_MAC1_ADDR_LO, 0xffffffff);
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CHECK_REG32(NPCM_GMAC_MAC2_ADDR_HI, 0x0000ffff);
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CHECK_REG32(NPCM_GMAC_MAC2_ADDR_LO, 0xffffffff);
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CHECK_REG32(NPCM_GMAC_MAC3_ADDR_HI, 0x0000ffff);
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CHECK_REG32(NPCM_GMAC_MAC3_ADDR_LO, 0xffffffff);
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CHECK_REG32(NPCM_GMAC_RGMII_STATUS, 0);
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CHECK_REG32(NPCM_GMAC_WATCHDOG, 0);
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CHECK_REG32(NPCM_GMAC_PTP_TCR, 0x00002000);
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CHECK_REG32(NPCM_GMAC_PTP_SSIR, 0);
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CHECK_REG32(NPCM_GMAC_PTP_STSR, 0);
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CHECK_REG32(NPCM_GMAC_PTP_STNSR, 0);
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CHECK_REG32(NPCM_GMAC_PTP_STSUR, 0);
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CHECK_REG32(NPCM_GMAC_PTP_STNSUR, 0);
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CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
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CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
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/* TODO Add registers PCS */
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if (mod->base_addr == 0xf0802000) {
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CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
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CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
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CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
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CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
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}
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qtest_quit(qts);
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}
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static void gmac_add_test(const char *name, const TestData* td,
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GTestDataFunc fn)
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{
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g_autofree char *full_name = g_strdup_printf(
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"npcm7xx_gmac/gmac[%d]/%s", gmac_module_index(td->module), name);
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qtest_add_data_func(full_name, td, fn);
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}
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int main(int argc, char **argv)
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{
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TestData test_data_list[ARRAY_SIZE(gmac_module_list)];
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g_test_init(&argc, &argv, NULL);
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for (int i = 0; i < ARRAY_SIZE(gmac_module_list); ++i) {
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TestData *td = &test_data_list[i];
|
|
|
|
td->module = &gmac_module_list[i];
|
|
|
|
gmac_add_test("init", td, test_init);
|
|
}
|
|
|
|
return g_test_run();
|
|
}
|