668f62ec62
When all we do with an Error we receive into a local variable is
propagating to somewhere else, we can just as well receive it there
right away. Convert
if (!foo(..., &err)) {
...
error_propagate(errp, err);
...
return ...
}
to
if (!foo(..., errp)) {
...
...
return ...
}
where nothing else needs @err. Coccinelle script:
@rule1 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
binary operator op;
constant c1, c2;
symbol false;
@@
if (
(
- fun(args, &err, args2)
+ fun(args, errp, args2)
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- !fun(args, &err, args2)
+ !fun(args, errp, args2)
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- fun(args, &err, args2) op c1
+ fun(args, errp, args2) op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
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return c2;
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return false;
)
}
@rule2 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
expression var;
binary operator op;
constant c1, c2;
symbol false;
@@
- var = fun(args, &err, args2);
+ var = fun(args, errp, args2);
... when != err
if (
(
var
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!var
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var op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
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return c2;
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return false;
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return var;
)
}
@depends on rule1 || rule2@
identifier err;
@@
- Error *err = NULL;
... when != err
Not exactly elegant, I'm afraid.
The "when != lbl:" is necessary to avoid transforming
if (fun(args, &err)) {
goto out
}
...
out:
error_propagate(errp, err);
even though other paths to label out still need the error_propagate().
For an actual example, see sclp_realize().
Without the "when strict", Coccinelle transforms vfio_msix_setup(),
incorrectly. I don't know what exactly "when strict" does, only that
it helps here.
The match of return is narrower than what I want, but I can't figure
out how to express "return where the operand doesn't use @err". For
an example where it's too narrow, see vfio_intx_enable().
Silently fails to convert hw/arm/armsse.c, because Coccinelle gets
confused by ARMSSE being used both as typedef and function-like macro
there. Converted manually.
Line breaks tidied up manually. One nested declaration of @local_err
deleted manually. Preexisting unwanted blank line dropped in
hw/riscv/sifive_e.c.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20200707160613.848843-35-armbru@redhat.com>
181 lines
6.5 KiB
C
181 lines
6.5 KiB
C
/*
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* Cortex-A15MPCore internal peripheral emulation.
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*
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* Copyright (c) 2012 Linaro Limited.
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* Written by Peter Maydell.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/cpu/a15mpcore.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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static void a15mp_priv_set_irq(void *opaque, int irq, int level)
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{
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A15MPPrivState *s = (A15MPPrivState *)opaque;
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qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
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}
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static void a15mp_priv_initfn(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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A15MPPrivState *s = A15MPCORE_PRIV(obj);
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memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
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sysbus_init_mmio(sbd, &s->container);
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object_initialize_child(obj, "gic", &s->gic, gic_class_name());
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qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
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}
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static void a15mp_priv_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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A15MPPrivState *s = A15MPCORE_PRIV(dev);
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DeviceState *gicdev;
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SysBusDevice *busdev;
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int i;
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bool has_el3;
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bool has_el2 = false;
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Object *cpuobj;
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gicdev = DEVICE(&s->gic);
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qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
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qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
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if (!kvm_irqchip_in_kernel()) {
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/* Make the GIC's TZ support match the CPUs. We assume that
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* either all the CPUs have TZ, or none do.
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*/
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cpuobj = OBJECT(qemu_get_cpu(0));
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has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
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object_property_get_bool(cpuobj, "has_el3", &error_abort);
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qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
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/* Similarly for virtualization support */
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has_el2 = object_property_find(cpuobj, "has_el2", NULL) &&
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object_property_get_bool(cpuobj, "has_el2", &error_abort);
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qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2);
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}
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
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return;
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}
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busdev = SYS_BUS_DEVICE(&s->gic);
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/* Pass through outbound IRQ lines from the GIC */
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sysbus_pass_irq(sbd, busdev);
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/* Pass through inbound GPIO lines to the GIC */
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qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
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/* Wire the outputs from each CPU's generic timer to the
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* appropriate GIC PPI inputs
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*/
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for (i = 0; i < s->num_cpu; i++) {
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DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
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int ppibase = s->num_irq - 32 + i * 32;
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int irq;
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/* Mapping from the output timer irq lines from the CPU to the
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* GIC PPI inputs used on the A15:
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*/
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const int timer_irq[] = {
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[GTIMER_PHYS] = 30,
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[GTIMER_VIRT] = 27,
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[GTIMER_HYP] = 26,
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[GTIMER_SEC] = 29,
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};
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for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
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qdev_connect_gpio_out(cpudev, irq,
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qdev_get_gpio_in(gicdev,
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ppibase + timer_irq[irq]));
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}
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if (has_el2) {
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/* Connect the GIC maintenance interrupt to PPI ID 25 */
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sysbus_connect_irq(SYS_BUS_DEVICE(gicdev), i + 4 * s->num_cpu,
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qdev_get_gpio_in(gicdev, ppibase + 25));
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}
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}
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/* Memory map (addresses are offsets from PERIPHBASE):
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* 0x0000-0x0fff -- reserved
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* 0x1000-0x1fff -- GIC Distributor
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* 0x2000-0x3fff -- GIC CPU interface
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* 0x4000-0x4fff -- GIC virtual interface control for this CPU
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* 0x5000-0x51ff -- GIC virtual interface control for CPU 0
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* 0x5200-0x53ff -- GIC virtual interface control for CPU 1
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* 0x5400-0x55ff -- GIC virtual interface control for CPU 2
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* 0x5600-0x57ff -- GIC virtual interface control for CPU 3
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* 0x6000-0x7fff -- GIC virtual CPU interface
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*/
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memory_region_add_subregion(&s->container, 0x1000,
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sysbus_mmio_get_region(busdev, 0));
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memory_region_add_subregion(&s->container, 0x2000,
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sysbus_mmio_get_region(busdev, 1));
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if (has_el2) {
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memory_region_add_subregion(&s->container, 0x4000,
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sysbus_mmio_get_region(busdev, 2));
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memory_region_add_subregion(&s->container, 0x6000,
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sysbus_mmio_get_region(busdev, 3));
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for (i = 0; i < s->num_cpu; i++) {
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hwaddr base = 0x5000 + i * 0x200;
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MemoryRegion *mr = sysbus_mmio_get_region(busdev,
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4 + s->num_cpu + i);
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memory_region_add_subregion(&s->container, base, mr);
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}
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}
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}
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static Property a15mp_priv_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
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/* The Cortex-A15MP may have anything from 0 to 224 external interrupt
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* IRQ lines (with another 32 internal). We default to 128+32, which
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* is the number provided by the Cortex-A15MP test chip in the
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* Versatile Express A15 development board.
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* Other boards may differ and should set this property appropriately.
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*/
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DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void a15mp_priv_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = a15mp_priv_realize;
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device_class_set_props(dc, a15mp_priv_properties);
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/* We currently have no savable state */
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}
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static const TypeInfo a15mp_priv_info = {
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.name = TYPE_A15MPCORE_PRIV,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(A15MPPrivState),
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.instance_init = a15mp_priv_initfn,
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.class_init = a15mp_priv_class_init,
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};
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static void a15mp_register_types(void)
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{
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type_register_static(&a15mp_priv_info);
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}
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type_init(a15mp_register_types)
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