10df8ff146
MX interrupt controller is a collection of the following devices accessible through the external registers interface: - interrupt distributor can route each external IRQ line to the corresponding external IRQ pin of selected subset of connected xtensa cores. It has per-CPU and per-IRQ enable signals and per-IRQ software assert signals; - IPI controller has 16 per-CPU IPI signals that may be routed to a combination of 3 designated external IRQ pins of connected xtensa cores; - cache coherecy register controls core L1 cache participation in the SMP cluster cache coherency protocol; - runstall register lets BSP core stall and unstall AP cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
6 lines
95 B
Makefile
6 lines
95 B
Makefile
obj-y += mx_pic.o
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obj-y += pic_cpu.o
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obj-y += sim.o
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obj-y += xtensa_memory.o
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obj-y += xtfpga.o
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