qemu-e2k/hw/riscv
Bin Meng d6150ace2b hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.

With this commit, HSS image built from 2020.12 release boots again.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-22 21:54:40 -04:00
..
boot.c
Kconfig hw/riscv: Add fw_cfg support to virt 2021-03-22 21:54:40 -04:00
meson.build
microchip_pfsoc.c hw/riscv: microchip_pfsoc: Map EMMC/SD mux register 2021-03-22 21:54:40 -04:00
numa.c
opentitan.c hw/riscv: Drop 'struct MemmapEntry' 2021-03-04 09:43:29 -05:00
riscv_hart.c
sifive_e.c hw/riscv: Drop 'struct MemmapEntry' 2021-03-04 09:43:29 -05:00
sifive_u.c hw/riscv: Drop 'struct MemmapEntry' 2021-03-04 09:43:29 -05:00
spike.c qtest: delete superfluous inclusions of qtest.h 2021-03-09 06:03:53 +01:00
virt.c hw/riscv: allow ramfb on virt 2021-03-22 21:54:40 -04:00