Bastian Koppelmann 12f323e66e target-tricore: Add instructions of RR2 opcode format ...

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>

2015-01-27 11:48:02 +00:00

..

cpu-qom.h

target-tricore: Remove the dummy interrupt boilerplate

2014-09-25 18:54:22 +01:00

cpu.c

target-tricore: Several translator and cpu model fixes

2015-01-26 19:56:45 +00:00

cpu.h

target-tricore: Fix bugs found by coverity

2015-01-26 19:56:45 +00:00

csfr.def

target-tricore: Fix new typos

2015-01-15 10:44:13 +03:00

helper.c

target-tricore: Remove the dummy interrupt boilerplate

2014-09-25 18:54:22 +01:00

helper.h

target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode

2014-12-21 18:35:49 +00:00

Makefile.objs

…

op_helper.c

target-tricore: split up suov32 into suov32_pos and suov32_neg

2015-01-26 19:56:46 +00:00

translate.c

target-tricore: Add instructions of RR2 opcode format

2015-01-27 11:48:02 +00:00

tricore-defs.h

…

tricore-opcodes.h

target-tricore: Fix new typos

2015-01-15 10:44:13 +03:00