Richard Henderson 133b84c819 target-tilegx: Handle nofault prefetch instructions ... These are mapped onto some of the normal load instructions, when the destination is the zero register. Other load insns do fault even when targeting the zero register. Signed-off-by: Richard Henderson <rth@twiddle.net>		2015-10-07 20:03:16 +11:00
..
cpu.c	target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV	2015-10-07 20:03:15 +11:00
cpu.h	target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV	2015-10-07 20:03:15 +11:00
helper.c	target-tilegx: Implement complex multiply instructions	2015-10-07 20:03:14 +11:00
helper.h	target-tilegx: Implement complex multiply instructions	2015-10-07 20:03:14 +11:00
Makefile.objs	target-tilegx: Handle v1shl, v1shru, v1shrs	2015-09-15 07:45:34 -07:00
opcode_tilegx.h	target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1	2015-09-15 07:41:35 -07:00
simd_helper.c	target-tilegx: Implement v1multu instruction	2015-10-07 20:03:14 +11:00
spr_def_64.h	target-tilegx: Add special register information from Tilera Corporation	2015-09-15 07:41:35 -07:00
translate.c	target-tilegx: Handle nofault prefetch instructions	2015-10-07 20:03:16 +11:00