551 lines
16 KiB
C
551 lines
16 KiB
C
/*
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* QEMU PowerPC E500 embedded processors pci controller emulation
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*
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* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Yu Liu, <yu.liu@freescale.com>
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*
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* This file is derived from hw/ppc4xx_pci.c,
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* the copyright for that material belongs to the original owners.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/ppc/e500-ccsr.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "qemu/bswap.h"
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#include "hw/pci-host/ppce500.h"
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#ifdef DEBUG_PCI
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#define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
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#else
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#define pci_debug(fmt, ...)
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#endif
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#define PCIE500_CFGADDR 0x0
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#define PCIE500_CFGDATA 0x4
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#define PCIE500_REG_BASE 0xC00
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#define PCIE500_ALL_SIZE 0x1000
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#define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
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#define PCIE500_PCI_IOLEN 0x10000ULL
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#define PPCE500_PCI_CONFIG_ADDR 0x0
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#define PPCE500_PCI_CONFIG_DATA 0x4
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#define PPCE500_PCI_INTACK 0x8
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#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
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#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
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#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
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#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
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#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
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#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
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#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
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#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
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#define PCI_POTAR 0x0
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#define PCI_POTEAR 0x4
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#define PCI_POWBAR 0x8
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#define PCI_POWAR 0x10
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#define PCI_PITAR 0x0
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#define PCI_PIWBAR 0x8
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#define PCI_PIWBEAR 0xC
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#define PCI_PIWAR 0x10
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#define PPCE500_PCI_NR_POBS 5
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#define PPCE500_PCI_NR_PIBS 3
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#define PIWAR_EN 0x80000000 /* Enable */
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#define PIWAR_PF 0x20000000 /* prefetch */
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#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
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#define PIWAR_READ_SNOOP 0x00050000
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#define PIWAR_WRITE_SNOOP 0x00005000
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#define PIWAR_SZ_MASK 0x0000003f
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struct pci_outbound {
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uint32_t potar;
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uint32_t potear;
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uint32_t powbar;
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uint32_t powar;
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MemoryRegion mem;
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};
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struct pci_inbound {
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uint32_t pitar;
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uint32_t piwbar;
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uint32_t piwbear;
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uint32_t piwar;
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MemoryRegion mem;
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};
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#define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
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#define PPC_E500_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
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struct PPCE500PCIState {
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PCIHostState parent_obj;
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struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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uint32_t gasket_time;
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qemu_irq irq[PCI_NUM_PINS];
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uint32_t irq_num[PCI_NUM_PINS];
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uint32_t first_slot;
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uint32_t first_pin_irq;
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AddressSpace bm_as;
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MemoryRegion bm;
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/* mmio maps */
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MemoryRegion container;
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MemoryRegion iomem;
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MemoryRegion pio;
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MemoryRegion busmem;
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};
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#define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
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#define PPC_E500_PCI_BRIDGE(obj) \
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OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
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struct PPCE500PCIBridgeState {
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/*< private >*/
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PCIDevice parent;
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/*< public >*/
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MemoryRegion bar0;
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};
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typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
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typedef struct PPCE500PCIState PPCE500PCIState;
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static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
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unsigned size)
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{
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PPCE500PCIState *pci = opaque;
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unsigned long win;
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uint32_t value = 0;
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int idx;
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win = addr & 0xfe0;
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switch (win) {
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case PPCE500_PCI_OW1:
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case PPCE500_PCI_OW2:
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case PPCE500_PCI_OW3:
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case PPCE500_PCI_OW4:
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idx = (addr >> 5) & 0x7;
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switch (addr & 0x1F) {
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case PCI_POTAR:
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value = pci->pob[idx].potar;
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break;
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case PCI_POTEAR:
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value = pci->pob[idx].potear;
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break;
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case PCI_POWBAR:
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value = pci->pob[idx].powbar;
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break;
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case PCI_POWAR:
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value = pci->pob[idx].powar;
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break;
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default:
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break;
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}
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break;
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case PPCE500_PCI_IW3:
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case PPCE500_PCI_IW2:
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case PPCE500_PCI_IW1:
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idx = ((addr >> 5) & 0x3) - 1;
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switch (addr & 0x1F) {
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case PCI_PITAR:
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value = pci->pib[idx].pitar;
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break;
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case PCI_PIWBAR:
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value = pci->pib[idx].piwbar;
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break;
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case PCI_PIWBEAR:
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value = pci->pib[idx].piwbear;
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break;
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case PCI_PIWAR:
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value = pci->pib[idx].piwar;
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break;
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default:
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break;
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};
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break;
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case PPCE500_PCI_GASKET_TIMR:
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value = pci->gasket_time;
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break;
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default:
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break;
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}
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pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
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win, addr, value);
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return value;
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}
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/* DMA mapping */
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static void e500_update_piw(PPCE500PCIState *pci, int idx)
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{
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uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12;
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uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12;
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uint64_t war = pci->pib[idx].piwar;
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uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *mem = &pci->pib[idx].mem;
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MemoryRegion *bm = &pci->bm;
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char *name;
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if (memory_region_is_mapped(mem)) {
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/* Before we modify anything, unmap and destroy the region */
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memory_region_del_subregion(bm, mem);
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object_unparent(OBJECT(mem));
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}
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if (!(war & PIWAR_EN)) {
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/* Not enabled, nothing to do */
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return;
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}
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name = g_strdup_printf("PCI Inbound Window %d", idx);
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memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar,
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size);
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memory_region_add_subregion_overlap(bm, wbar, mem, -1);
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g_free(name);
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pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n",
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__func__, size, wbar, tar);
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}
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/* BAR mapping */
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static void e500_update_pow(PPCE500PCIState *pci, int idx)
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{
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uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12;
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uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12;
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uint64_t war = pci->pob[idx].powar;
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uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
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MemoryRegion *mem = &pci->pob[idx].mem;
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MemoryRegion *address_space_mem = get_system_memory();
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char *name;
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if (memory_region_is_mapped(mem)) {
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/* Before we modify anything, unmap and destroy the region */
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memory_region_del_subregion(address_space_mem, mem);
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object_unparent(OBJECT(mem));
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}
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if (!(war & PIWAR_EN)) {
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/* Not enabled, nothing to do */
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return;
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}
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name = g_strdup_printf("PCI Outbound Window %d", idx);
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memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar,
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size);
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memory_region_add_subregion(address_space_mem, wbar, mem);
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g_free(name);
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pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n",
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__func__, size, wbar, tar);
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}
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static void pci_reg_write4(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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PPCE500PCIState *pci = opaque;
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unsigned long win;
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int idx;
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win = addr & 0xfe0;
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pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
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__func__, (unsigned)value, win, addr);
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switch (win) {
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case PPCE500_PCI_OW1:
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case PPCE500_PCI_OW2:
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case PPCE500_PCI_OW3:
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case PPCE500_PCI_OW4:
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idx = (addr >> 5) & 0x7;
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switch (addr & 0x1F) {
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case PCI_POTAR:
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pci->pob[idx].potar = value;
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e500_update_pow(pci, idx);
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break;
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case PCI_POTEAR:
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pci->pob[idx].potear = value;
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e500_update_pow(pci, idx);
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break;
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case PCI_POWBAR:
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pci->pob[idx].powbar = value;
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e500_update_pow(pci, idx);
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break;
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case PCI_POWAR:
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pci->pob[idx].powar = value;
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e500_update_pow(pci, idx);
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break;
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default:
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break;
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};
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break;
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case PPCE500_PCI_IW3:
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case PPCE500_PCI_IW2:
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case PPCE500_PCI_IW1:
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idx = ((addr >> 5) & 0x3) - 1;
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switch (addr & 0x1F) {
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case PCI_PITAR:
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pci->pib[idx].pitar = value;
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e500_update_piw(pci, idx);
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break;
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case PCI_PIWBAR:
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pci->pib[idx].piwbar = value;
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e500_update_piw(pci, idx);
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break;
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case PCI_PIWBEAR:
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pci->pib[idx].piwbear = value;
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e500_update_piw(pci, idx);
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break;
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case PCI_PIWAR:
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pci->pib[idx].piwar = value;
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e500_update_piw(pci, idx);
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break;
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default:
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break;
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};
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break;
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case PPCE500_PCI_GASKET_TIMR:
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pci->gasket_time = value;
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break;
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default:
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break;
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};
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}
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static const MemoryRegionOps e500_pci_reg_ops = {
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.read = pci_reg_read4,
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.write = pci_reg_write4,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
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{
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int devno = pci_dev->devfn >> 3;
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int ret;
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ret = ppce500_pci_map_irq_slot(devno, pin);
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pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
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pci_dev->devfn, pin, ret, devno);
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return ret;
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}
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static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
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{
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PPCE500PCIState *s = opaque;
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qemu_irq *pic = s->irq;
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pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);
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qemu_set_irq(pic[pin], level);
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}
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static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin)
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{
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PCIINTxRoute route;
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PPCE500PCIState *s = opaque;
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route.mode = PCI_INTX_ENABLED;
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route.irq = s->irq_num[pin];
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pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq);
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return route;
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}
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static const VMStateDescription vmstate_pci_outbound = {
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.name = "pci_outbound",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(potar, struct pci_outbound),
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VMSTATE_UINT32(potear, struct pci_outbound),
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VMSTATE_UINT32(powbar, struct pci_outbound),
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VMSTATE_UINT32(powar, struct pci_outbound),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_pci_inbound = {
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.name = "pci_inbound",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(pitar, struct pci_inbound),
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VMSTATE_UINT32(piwbar, struct pci_inbound),
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VMSTATE_UINT32(piwbear, struct pci_inbound),
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VMSTATE_UINT32(piwar, struct pci_inbound),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_ppce500_pci = {
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.name = "ppce500_pci",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
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vmstate_pci_outbound, struct pci_outbound),
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VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
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vmstate_pci_inbound, struct pci_inbound),
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VMSTATE_UINT32(gasket_time, PPCE500PCIState),
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VMSTATE_END_OF_LIST()
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}
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};
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#include "exec/address-spaces.h"
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static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
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{
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PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
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PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
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"/e500-ccsr"));
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memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
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0, int128_get64(ccsr->ccsr_space.size));
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pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
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}
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static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
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int devfn)
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{
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PPCE500PCIState *s = opaque;
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return &s->bm_as;
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}
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static int e500_pcihost_initfn(SysBusDevice *dev)
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{
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PCIHostState *h;
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PPCE500PCIState *s;
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PCIBus *b;
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int i;
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h = PCI_HOST_BRIDGE(dev);
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s = PPC_E500_PCI_HOST_BRIDGE(dev);
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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for (i = 0; i < PCI_NUM_PINS; i++) {
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s->irq_num[i] = s->first_pin_irq + i;
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}
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memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);
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memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX);
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/* PIO lives at the bottom of our bus space */
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memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2);
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b = pci_register_root_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
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mpc85xx_pci_map_irq, s, &s->busmem, &s->pio,
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PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
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h->bus = b;
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/* Set up PCI view of memory */
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memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX);
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memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
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address_space_init(&s->bm_as, &s->bm, "pci-bm");
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pci_setup_iommu(b, e500_pcihost_set_iommu, s);
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pci_create_simple(b, 0, "e500-host-bridge");
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memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
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memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
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"pci-conf-idx", 4);
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memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h,
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"pci-conf-data", 4);
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memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s,
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"pci.reg", PCIE500_REG_SIZE);
|
|
memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
|
|
memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
|
|
memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
|
|
sysbus_init_mmio(dev, &s->container);
|
|
pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->realize = e500_pcihost_bridge_realize;
|
|
k->vendor_id = PCI_VENDOR_ID_FREESCALE;
|
|
k->device_id = PCI_DEVICE_ID_MPC8533E;
|
|
k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
|
|
dc->desc = "Host bridge";
|
|
/*
|
|
* PCI-facing part of the host bridge, not usable without the
|
|
* host-facing part, which can't be device_add'ed, yet.
|
|
*/
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo e500_host_bridge_info = {
|
|
.name = "e500-host-bridge",
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(PPCE500PCIBridgeState),
|
|
.class_init = e500_host_bridge_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
{ },
|
|
},
|
|
};
|
|
|
|
static Property pcihost_properties[] = {
|
|
DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
|
|
DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void e500_pcihost_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
k->init = e500_pcihost_initfn;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
dc->props = pcihost_properties;
|
|
dc->vmsd = &vmstate_ppce500_pci;
|
|
}
|
|
|
|
static const TypeInfo e500_pcihost_info = {
|
|
.name = TYPE_PPC_E500_PCI_HOST_BRIDGE,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(PPCE500PCIState),
|
|
.class_init = e500_pcihost_class_init,
|
|
};
|
|
|
|
static void e500_pci_register_types(void)
|
|
{
|
|
type_register_static(&e500_pcihost_info);
|
|
type_register_static(&e500_host_bridge_info);
|
|
}
|
|
|
|
type_init(e500_pci_register_types)
|