698 lines
24 KiB
C
698 lines
24 KiB
C
/*
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* QEMU PowerPC pSeries Logical Partition NUMA associativity handling
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*
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* Copyright IBM Corp. 2020
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*
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* Authors:
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* Daniel Henrique Barboza <danielhb413@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "hw/ppc/spapr_numa.h"
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#include "hw/pci-host/spapr.h"
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#include "hw/ppc/fdt.h"
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/* Moved from hw/ppc/spapr_pci_nvlink2.c */
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#define SPAPR_GPU_NUMA_ID (cpu_to_be32(1))
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/*
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* Retrieves max_dist_ref_points of the current NUMA affinity.
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*/
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static int get_max_dist_ref_points(SpaprMachineState *spapr)
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{
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if (spapr_ovec_test(spapr->ov5_cas, OV5_FORM2_AFFINITY)) {
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return FORM2_DIST_REF_POINTS;
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}
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return FORM1_DIST_REF_POINTS;
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}
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/*
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* Retrieves numa_assoc_size of the current NUMA affinity.
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*/
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static int get_numa_assoc_size(SpaprMachineState *spapr)
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{
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if (spapr_ovec_test(spapr->ov5_cas, OV5_FORM2_AFFINITY)) {
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return FORM2_NUMA_ASSOC_SIZE;
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}
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return FORM1_NUMA_ASSOC_SIZE;
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}
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/*
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* Retrieves vcpu_assoc_size of the current NUMA affinity.
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*
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* vcpu_assoc_size is the size of ibm,associativity array
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* for CPUs, which has an extra element (vcpu_id) in the end.
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*/
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static int get_vcpu_assoc_size(SpaprMachineState *spapr)
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{
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return get_numa_assoc_size(spapr) + 1;
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}
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/*
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* Retrieves the ibm,associativity array of NUMA node 'node_id'
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* for the current NUMA affinity.
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*/
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static const uint32_t *get_associativity(SpaprMachineState *spapr, int node_id)
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{
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if (spapr_ovec_test(spapr->ov5_cas, OV5_FORM2_AFFINITY)) {
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return spapr->FORM2_assoc_array[node_id];
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}
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return spapr->FORM1_assoc_array[node_id];
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}
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/*
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* Wrapper that returns node distance from ms->numa_state->nodes
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* after handling edge cases where the distance might be absent.
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*/
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static int get_numa_distance(MachineState *ms, int src, int dst)
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{
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NodeInfo *numa_info = ms->numa_state->nodes;
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int ret = numa_info[src].distance[dst];
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if (ret != 0) {
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return ret;
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}
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/*
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* In case QEMU adds a default NUMA single node when the user
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* did not add any, or where the user did not supply distances,
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* the distance will be absent (zero). Return local/remote
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* distance in this case.
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*/
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if (src == dst) {
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return NUMA_DISTANCE_MIN;
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}
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return NUMA_DISTANCE_DEFAULT;
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}
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static bool spapr_numa_is_symmetrical(MachineState *ms)
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{
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int nb_numa_nodes = ms->numa_state->num_nodes;
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int src, dst;
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for (src = 0; src < nb_numa_nodes; src++) {
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for (dst = src; dst < nb_numa_nodes; dst++) {
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if (get_numa_distance(ms, src, dst) !=
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get_numa_distance(ms, dst, src)) {
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return false;
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}
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}
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}
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return true;
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}
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/*
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* NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
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* We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
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* called from vPHB reset handler so we initialize the counter here.
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* If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
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* must be equally distant from any other node.
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* The final value of spapr->gpu_numa_id is going to be written to
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* max-associativity-domains in spapr_build_fdt().
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*/
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unsigned int spapr_numa_initial_nvgpu_numa_id(MachineState *machine)
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{
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return MAX(1, machine->numa_state->num_nodes);
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}
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/*
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* This function will translate the user distances into
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* what the kernel understand as possible values: 10
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* (local distance), 20, 40, 80 and 160, and return the equivalent
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* NUMA level for each. Current heuristic is:
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* - local distance (10) returns numa_level = 0x4, meaning there is
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* no rounding for local distance
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* - distances between 11 and 30 inclusive -> rounded to 20,
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* numa_level = 0x3
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* - distances between 31 and 60 inclusive -> rounded to 40,
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* numa_level = 0x2
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* - distances between 61 and 120 inclusive -> rounded to 80,
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* numa_level = 0x1
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* - everything above 120 returns numa_level = 0 to indicate that
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* there is no match. This will be calculated as disntace = 160
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* by the kernel (as of v5.9)
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*/
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static uint8_t spapr_numa_get_numa_level(uint8_t distance)
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{
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if (distance == 10) {
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return 0x4;
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} else if (distance > 11 && distance <= 30) {
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return 0x3;
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} else if (distance > 31 && distance <= 60) {
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return 0x2;
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} else if (distance > 61 && distance <= 120) {
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return 0x1;
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}
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return 0;
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}
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static void spapr_numa_define_FORM1_domains(SpaprMachineState *spapr)
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{
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MachineState *ms = MACHINE(spapr);
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int nb_numa_nodes = ms->numa_state->num_nodes;
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int src, dst, i, j;
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/*
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* Fill all associativity domains of non-zero NUMA nodes with
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* node_id. This is required because the default value (0) is
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* considered a match with associativity domains of node 0.
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*/
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for (i = 1; i < nb_numa_nodes; i++) {
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for (j = 1; j < FORM1_DIST_REF_POINTS; j++) {
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spapr->FORM1_assoc_array[i][j] = cpu_to_be32(i);
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}
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}
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for (src = 0; src < nb_numa_nodes; src++) {
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for (dst = src; dst < nb_numa_nodes; dst++) {
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/*
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* This is how the associativity domain between A and B
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* is calculated:
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*
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* - get the distance D between them
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* - get the correspondent NUMA level 'n_level' for D
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* - all associativity arrays were initialized with their own
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* numa_ids, and we're calculating the distance in node_id
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* ascending order, starting from node id 0 (the first node
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* retrieved by numa_state). This will have a cascade effect in
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* the algorithm because the associativity domains that node 0
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* defines will be carried over to other nodes, and node 1
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* associativities will be carried over after taking node 0
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* associativities into account, and so on. This happens because
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* we'll assign assoc_src as the associativity domain of dst
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* as well, for all NUMA levels beyond and including n_level.
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*
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* The PPC kernel expects the associativity domains of node 0 to
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* be always 0, and this algorithm will grant that by default.
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*/
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uint8_t distance = get_numa_distance(ms, src, dst);
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uint8_t n_level = spapr_numa_get_numa_level(distance);
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uint32_t assoc_src;
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/*
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* n_level = 0 means that the distance is greater than our last
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* rounded value (120). In this case there is no NUMA level match
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* between src and dst and we can skip the remaining of the loop.
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*
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* The Linux kernel will assume that the distance between src and
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* dst, in this case of no match, is 10 (local distance) doubled
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* for each NUMA it didn't match. We have FORM1_DIST_REF_POINTS
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* levels (4), so this gives us 10*2*2*2*2 = 160.
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*
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* This logic can be seen in the Linux kernel source code, as of
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* v5.9, in arch/powerpc/mm/numa.c, function __node_distance().
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*/
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if (n_level == 0) {
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continue;
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}
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/*
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* We must assign all assoc_src to dst, starting from n_level
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* and going up to 0x1.
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*/
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for (i = n_level; i > 0; i--) {
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assoc_src = spapr->FORM1_assoc_array[src][i];
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spapr->FORM1_assoc_array[dst][i] = assoc_src;
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}
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}
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}
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}
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static void spapr_numa_FORM1_affinity_check(MachineState *machine)
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{
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int i;
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/*
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* Check we don't have a memory-less/cpu-less NUMA node
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* Firmware relies on the existing memory/cpu topology to provide the
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* NUMA topology to the kernel.
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* And the linux kernel needs to know the NUMA topology at start
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* to be able to hotplug CPUs later.
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*/
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if (machine->numa_state->num_nodes) {
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for (i = 0; i < machine->numa_state->num_nodes; ++i) {
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/* check for memory-less node */
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if (machine->numa_state->nodes[i].node_mem == 0) {
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CPUState *cs;
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int found = 0;
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/* check for cpu-less node */
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CPU_FOREACH(cs) {
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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if (cpu->node_id == i) {
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found = 1;
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break;
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}
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}
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/* memory-less and cpu-less node */
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if (!found) {
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error_report(
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"Memory-less/cpu-less nodes are not supported with FORM1 NUMA (node %d)", i);
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exit(EXIT_FAILURE);
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}
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}
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}
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}
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if (!spapr_numa_is_symmetrical(machine)) {
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error_report(
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"Asymmetrical NUMA topologies aren't supported in the pSeries machine using FORM1 NUMA");
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exit(EXIT_FAILURE);
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}
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}
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/*
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* Set NUMA machine state data based on FORM1 affinity semantics.
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*/
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static void spapr_numa_FORM1_affinity_init(SpaprMachineState *spapr,
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MachineState *machine)
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{
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SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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int nb_numa_nodes = machine->numa_state->num_nodes;
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int i, j, max_nodes_with_gpus;
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/*
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* For all associativity arrays: first position is the size,
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* position FORM1_DIST_REF_POINTS is always the numa_id,
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* represented by the index 'i'.
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*
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* This will break on sparse NUMA setups, when/if QEMU starts
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* to support it, because there will be no more guarantee that
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* 'i' will be a valid node_id set by the user.
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*/
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for (i = 0; i < nb_numa_nodes; i++) {
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spapr->FORM1_assoc_array[i][0] = cpu_to_be32(FORM1_DIST_REF_POINTS);
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spapr->FORM1_assoc_array[i][FORM1_DIST_REF_POINTS] = cpu_to_be32(i);
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}
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/*
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* Initialize NVLink GPU associativity arrays. We know that
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* the first GPU will take the first available NUMA id, and
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* we'll have a maximum of NVGPU_MAX_NUM GPUs in the machine.
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* At this point we're not sure if there are GPUs or not, but
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* let's initialize the associativity arrays and allow NVLink
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* GPUs to be handled like regular NUMA nodes later on.
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*/
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max_nodes_with_gpus = nb_numa_nodes + NVGPU_MAX_NUM;
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for (i = nb_numa_nodes; i < max_nodes_with_gpus; i++) {
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spapr->FORM1_assoc_array[i][0] = cpu_to_be32(FORM1_DIST_REF_POINTS);
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for (j = 1; j < FORM1_DIST_REF_POINTS; j++) {
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uint32_t gpu_assoc = smc->pre_5_1_assoc_refpoints ?
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SPAPR_GPU_NUMA_ID : cpu_to_be32(i);
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spapr->FORM1_assoc_array[i][j] = gpu_assoc;
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}
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spapr->FORM1_assoc_array[i][FORM1_DIST_REF_POINTS] = cpu_to_be32(i);
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}
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/*
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* Guests pseries-5.1 and older uses zeroed associativity domains,
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* i.e. no domain definition based on NUMA distance input.
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*
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* Same thing with guests that have only one NUMA node.
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*/
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if (smc->pre_5_2_numa_associativity ||
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machine->numa_state->num_nodes <= 1) {
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return;
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}
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spapr_numa_define_FORM1_domains(spapr);
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}
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/*
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* Init NUMA FORM2 machine state data
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*/
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static void spapr_numa_FORM2_affinity_init(SpaprMachineState *spapr)
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{
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int i;
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/*
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* For all resources but CPUs, FORM2 associativity arrays will
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* be a size 2 array with the following format:
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*
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* ibm,associativity = {1, numa_id}
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*
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* CPUs will write an additional 'vcpu_id' on top of the arrays
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* being initialized here. 'numa_id' is represented by the
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* index 'i' of the loop.
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*
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* Given that this initialization is also valid for GPU associativity
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* arrays, handle everything in one single step by populating the
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* arrays up to NUMA_NODES_MAX_NUM.
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*/
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for (i = 0; i < NUMA_NODES_MAX_NUM; i++) {
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spapr->FORM2_assoc_array[i][0] = cpu_to_be32(1);
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spapr->FORM2_assoc_array[i][1] = cpu_to_be32(i);
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}
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}
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void spapr_numa_associativity_init(SpaprMachineState *spapr,
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MachineState *machine)
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{
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spapr_numa_FORM1_affinity_init(spapr, machine);
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spapr_numa_FORM2_affinity_init(spapr);
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}
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void spapr_numa_associativity_check(SpaprMachineState *spapr)
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{
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/*
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* FORM2 does not have any restrictions we need to handle
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* at CAS time, for now.
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*/
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if (spapr_ovec_test(spapr->ov5_cas, OV5_FORM2_AFFINITY)) {
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return;
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}
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spapr_numa_FORM1_affinity_check(MACHINE(spapr));
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}
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void spapr_numa_write_associativity_dt(SpaprMachineState *spapr, void *fdt,
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int offset, int nodeid)
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{
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const uint32_t *associativity = get_associativity(spapr, nodeid);
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_FDT((fdt_setprop(fdt, offset, "ibm,associativity",
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associativity,
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get_numa_assoc_size(spapr) * sizeof(uint32_t))));
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}
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static uint32_t *spapr_numa_get_vcpu_assoc(SpaprMachineState *spapr,
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PowerPCCPU *cpu)
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{
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const uint32_t *associativity = get_associativity(spapr, cpu->node_id);
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int max_distance_ref_points = get_max_dist_ref_points(spapr);
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int vcpu_assoc_size = get_vcpu_assoc_size(spapr);
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uint32_t *vcpu_assoc = g_new(uint32_t, vcpu_assoc_size);
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int index = spapr_get_vcpu_id(cpu);
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/*
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* VCPUs have an extra 'cpu_id' value in ibm,associativity
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* compared to other resources. Increment the size at index
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* 0, put cpu_id last, then copy the remaining associativity
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* domains.
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*/
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vcpu_assoc[0] = cpu_to_be32(max_distance_ref_points + 1);
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vcpu_assoc[vcpu_assoc_size - 1] = cpu_to_be32(index);
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memcpy(vcpu_assoc + 1, associativity + 1,
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(vcpu_assoc_size - 2) * sizeof(uint32_t));
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return vcpu_assoc;
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}
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int spapr_numa_fixup_cpu_dt(SpaprMachineState *spapr, void *fdt,
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int offset, PowerPCCPU *cpu)
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{
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g_autofree uint32_t *vcpu_assoc = NULL;
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int vcpu_assoc_size = get_vcpu_assoc_size(spapr);
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vcpu_assoc = spapr_numa_get_vcpu_assoc(spapr, cpu);
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/* Advertise NUMA via ibm,associativity */
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return fdt_setprop(fdt, offset, "ibm,associativity", vcpu_assoc,
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vcpu_assoc_size * sizeof(uint32_t));
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}
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int spapr_numa_write_assoc_lookup_arrays(SpaprMachineState *spapr, void *fdt,
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int offset)
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{
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MachineState *machine = MACHINE(spapr);
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int max_distance_ref_points = get_max_dist_ref_points(spapr);
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int nb_numa_nodes = machine->numa_state->num_nodes;
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int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
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g_autofree uint32_t *int_buf = NULL;
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uint32_t *cur_index;
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int i;
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/* ibm,associativity-lookup-arrays */
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int_buf = g_malloc0((nr_nodes * max_distance_ref_points + 2) *
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sizeof(uint32_t));
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cur_index = int_buf;
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int_buf[0] = cpu_to_be32(nr_nodes);
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/* Number of entries per associativity list */
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int_buf[1] = cpu_to_be32(max_distance_ref_points);
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cur_index += 2;
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for (i = 0; i < nr_nodes; i++) {
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/*
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* For the lookup-array we use the ibm,associativity array of the
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* current NUMA affinity, without the first element (size).
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*/
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const uint32_t *associativity = get_associativity(spapr, i);
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memcpy(cur_index, ++associativity,
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sizeof(uint32_t) * max_distance_ref_points);
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cur_index += max_distance_ref_points;
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}
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return fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays",
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int_buf, (cur_index - int_buf) * sizeof(uint32_t));
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}
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static void spapr_numa_FORM1_write_rtas_dt(SpaprMachineState *spapr,
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void *fdt, int rtas)
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{
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MachineState *ms = MACHINE(spapr);
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SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
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uint32_t number_nvgpus_nodes = spapr->gpu_numa_id -
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spapr_numa_initial_nvgpu_numa_id(ms);
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uint32_t refpoints[] = {
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cpu_to_be32(0x4),
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cpu_to_be32(0x3),
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cpu_to_be32(0x2),
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cpu_to_be32(0x1),
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};
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uint32_t nr_refpoints = ARRAY_SIZE(refpoints);
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uint32_t maxdomain = ms->numa_state->num_nodes + number_nvgpus_nodes;
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uint32_t maxdomains[] = {
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cpu_to_be32(4),
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cpu_to_be32(maxdomain),
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cpu_to_be32(maxdomain),
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cpu_to_be32(maxdomain),
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cpu_to_be32(maxdomain)
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};
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if (smc->pre_5_2_numa_associativity ||
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ms->numa_state->num_nodes <= 1) {
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uint32_t legacy_refpoints[] = {
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cpu_to_be32(0x4),
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cpu_to_be32(0x4),
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cpu_to_be32(0x2),
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};
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uint32_t legacy_maxdomain = spapr->gpu_numa_id > 1 ? 1 : 0;
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uint32_t legacy_maxdomains[] = {
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cpu_to_be32(4),
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cpu_to_be32(legacy_maxdomain),
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cpu_to_be32(legacy_maxdomain),
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cpu_to_be32(legacy_maxdomain),
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cpu_to_be32(spapr->gpu_numa_id),
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};
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G_STATIC_ASSERT(sizeof(legacy_refpoints) <= sizeof(refpoints));
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G_STATIC_ASSERT(sizeof(legacy_maxdomains) <= sizeof(maxdomains));
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nr_refpoints = 3;
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memcpy(refpoints, legacy_refpoints, sizeof(legacy_refpoints));
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memcpy(maxdomains, legacy_maxdomains, sizeof(legacy_maxdomains));
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/* pseries-5.0 and older reference-points array is {0x4, 0x4} */
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if (smc->pre_5_1_assoc_refpoints) {
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nr_refpoints = 2;
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}
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}
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_FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
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refpoints, nr_refpoints * sizeof(refpoints[0])));
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_FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
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maxdomains, sizeof(maxdomains)));
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}
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static void spapr_numa_FORM2_write_rtas_tables(SpaprMachineState *spapr,
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void *fdt, int rtas)
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{
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MachineState *ms = MACHINE(spapr);
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int nb_numa_nodes = ms->numa_state->num_nodes;
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int distance_table_entries = nb_numa_nodes * nb_numa_nodes;
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g_autofree uint32_t *lookup_index_table = NULL;
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g_autofree uint8_t *distance_table = NULL;
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int src, dst, i, distance_table_size;
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/*
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* ibm,numa-lookup-index-table: array with length and a
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* list of NUMA ids present in the guest.
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*/
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lookup_index_table = g_new0(uint32_t, nb_numa_nodes + 1);
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lookup_index_table[0] = cpu_to_be32(nb_numa_nodes);
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for (i = 0; i < nb_numa_nodes; i++) {
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lookup_index_table[i + 1] = cpu_to_be32(i);
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}
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_FDT(fdt_setprop(fdt, rtas, "ibm,numa-lookup-index-table",
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lookup_index_table,
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(nb_numa_nodes + 1) * sizeof(uint32_t)));
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/*
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* ibm,numa-distance-table: contains all node distances. First
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* element is the size of the table as uint32, followed up
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* by all the uint8 distances from the first NUMA node, then all
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* distances from the second NUMA node and so on.
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*
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* ibm,numa-lookup-index-table is used by guest to navigate this
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* array because NUMA ids can be sparse (node 0 is the first,
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* node 8 is the second ...).
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*/
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distance_table_size = distance_table_entries * sizeof(uint8_t) +
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sizeof(uint32_t);
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distance_table = g_new0(uint8_t, distance_table_size);
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stl_be_p(distance_table, distance_table_entries);
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/* Skip the uint32_t array length at the start */
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i = sizeof(uint32_t);
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for (src = 0; src < nb_numa_nodes; src++) {
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for (dst = 0; dst < nb_numa_nodes; dst++) {
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distance_table[i++] = get_numa_distance(ms, src, dst);
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}
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}
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_FDT(fdt_setprop(fdt, rtas, "ibm,numa-distance-table",
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distance_table, distance_table_size));
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}
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/*
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* This helper could be compressed in a single function with
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* FORM1 logic since we're setting the same DT values, with the
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* difference being a call to spapr_numa_FORM2_write_rtas_tables()
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* in the end. The separation was made to avoid clogging FORM1 code
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* which already has to deal with compat modes from previous
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* QEMU machine types.
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*/
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static void spapr_numa_FORM2_write_rtas_dt(SpaprMachineState *spapr,
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void *fdt, int rtas)
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{
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MachineState *ms = MACHINE(spapr);
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uint32_t number_nvgpus_nodes = spapr->gpu_numa_id -
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spapr_numa_initial_nvgpu_numa_id(ms);
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/*
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* In FORM2, ibm,associativity-reference-points will point to
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* the element in the ibm,associativity array that contains the
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* primary domain index (for FORM2, the first element).
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*
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* This value (in our case, the numa-id) is then used as an index
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* to retrieve all other attributes of the node (distance,
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* bandwidth, latency) via ibm,numa-lookup-index-table and other
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* ibm,numa-*-table properties.
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*/
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uint32_t refpoints[] = { cpu_to_be32(1) };
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uint32_t maxdomain = ms->numa_state->num_nodes + number_nvgpus_nodes;
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uint32_t maxdomains[] = { cpu_to_be32(1), cpu_to_be32(maxdomain) };
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_FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
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refpoints, sizeof(refpoints)));
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_FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
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maxdomains, sizeof(maxdomains)));
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spapr_numa_FORM2_write_rtas_tables(spapr, fdt, rtas);
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}
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/*
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* Helper that writes ibm,associativity-reference-points and
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* max-associativity-domains in the RTAS pointed by @rtas
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* in the DT @fdt.
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*/
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void spapr_numa_write_rtas_dt(SpaprMachineState *spapr, void *fdt, int rtas)
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{
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if (spapr_ovec_test(spapr->ov5_cas, OV5_FORM2_AFFINITY)) {
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spapr_numa_FORM2_write_rtas_dt(spapr, fdt, rtas);
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return;
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}
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spapr_numa_FORM1_write_rtas_dt(spapr, fdt, rtas);
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}
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static target_ulong h_home_node_associativity(PowerPCCPU *cpu,
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SpaprMachineState *spapr,
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target_ulong opcode,
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target_ulong *args)
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{
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g_autofree uint32_t *vcpu_assoc = NULL;
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target_ulong flags = args[0];
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target_ulong procno = args[1];
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PowerPCCPU *tcpu;
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int idx, assoc_idx;
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int vcpu_assoc_size = get_vcpu_assoc_size(spapr);
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/* only support procno from H_REGISTER_VPA */
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if (flags != 0x1) {
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return H_FUNCTION;
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}
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tcpu = spapr_find_cpu(procno);
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if (tcpu == NULL) {
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return H_P2;
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}
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/*
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* Given that we want to be flexible with the sizes and indexes,
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* we must consider that there is a hard limit of how many
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* associativities domain we can fit in R4 up to R9, which would be
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* 12 associativity domains for vcpus. Assert and bail if that's
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* not the case.
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*/
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g_assert((vcpu_assoc_size - 1) <= 12);
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vcpu_assoc = spapr_numa_get_vcpu_assoc(spapr, tcpu);
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/* assoc_idx starts at 1 to skip associativity size */
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assoc_idx = 1;
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#define ASSOCIATIVITY(a, b) (((uint64_t)(a) << 32) | \
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((uint64_t)(b) & 0xffffffff))
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for (idx = 0; idx < 6; idx++) {
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int32_t a, b;
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/*
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* vcpu_assoc[] will contain the associativity domains for tcpu,
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* including tcpu->node_id and procno, meaning that we don't
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* need to use these variables here.
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*
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* We'll read 2 values at a time to fill up the ASSOCIATIVITY()
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* macro. The ternary will fill the remaining registers with -1
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* after we went through vcpu_assoc[].
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*/
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a = assoc_idx < vcpu_assoc_size ?
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be32_to_cpu(vcpu_assoc[assoc_idx++]) : -1;
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b = assoc_idx < vcpu_assoc_size ?
|
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be32_to_cpu(vcpu_assoc[assoc_idx++]) : -1;
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args[idx] = ASSOCIATIVITY(a, b);
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}
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#undef ASSOCIATIVITY
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return H_SUCCESS;
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}
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static void spapr_numa_register_types(void)
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{
|
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/* Virtual Processor Home Node */
|
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spapr_register_hypercall(H_HOME_NODE_ASSOCIATIVITY,
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h_home_node_associativity);
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}
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type_init(spapr_numa_register_types)
|