qemu-e2k/target/riscv
Joel Sing c13b169f1a
RISC-V: Clear load reservations on context switch and SC
This prevents a load reservation from being placed in one context/process,
then being used in another, resulting in an SC succeeding incorrectly and
breaking atomics.

Signed-off-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-25 22:37:04 -07:00
..
insn_trans RISC-V: Clear load reservations on context switch and SC 2019-06-25 22:37:04 -07:00
cpu_bits.h
cpu_helper.c RISC-V: Clear load reservations on context switch and SC 2019-06-25 22:37:04 -07:00
cpu_user.h
cpu-param.h
cpu.c RISC-V: Clear load reservations on context switch and SC 2019-06-25 22:37:04 -07:00
cpu.h
csr.c
fpu_helper.c
gdbstub.c
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h
Makefile.objs
op_helper.c
pmp.c
pmp.h
trace-events
translate.c