144634ae6c
Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for register storage. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-12-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
1684 lines
62 KiB
C
1684 lines
62 KiB
C
/*
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* ARM virtual CPU header
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_ARM_H
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#define CPU_ARM_H
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#include "config.h"
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#include "kvm-consts.h"
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#if defined(TARGET_AARCH64)
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/* AArch64 definitions */
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# define TARGET_LONG_BITS 64
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# define ELF_MACHINE EM_AARCH64
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#else
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# define TARGET_LONG_BITS 32
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# define ELF_MACHINE EM_ARM
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#endif
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#define CPUArchState struct CPUARMState
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#include "qemu-common.h"
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat.h"
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#define TARGET_HAS_ICE 1
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#define EXCP_UDEF 1 /* undefined instruction */
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#define EXCP_SWI 2 /* software interrupt */
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#define EXCP_PREFETCH_ABORT 3
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#define EXCP_DATA_ABORT 4
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#define EXCP_IRQ 5
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#define EXCP_FIQ 6
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#define EXCP_BKPT 7
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#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
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#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
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#define EXCP_STREX 10
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#define EXCP_HVC 11 /* HyperVisor Call */
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#define EXCP_HYP_TRAP 12
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#define EXCP_SMC 13 /* Secure Monitor Call */
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#define EXCP_VIRQ 14
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#define EXCP_VFIQ 15
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#define ARMV7M_EXCP_RESET 1
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#define ARMV7M_EXCP_NMI 2
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#define ARMV7M_EXCP_HARD 3
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#define ARMV7M_EXCP_MEM 4
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#define ARMV7M_EXCP_BUS 5
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#define ARMV7M_EXCP_USAGE 6
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#define ARMV7M_EXCP_SVC 11
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#define ARMV7M_EXCP_DEBUG 12
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#define ARMV7M_EXCP_PENDSV 14
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#define ARMV7M_EXCP_SYSTICK 15
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/* ARM-specific interrupt pending bits. */
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#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
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#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
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#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
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/* The usual mapping for an AArch64 system register to its AArch32
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* counterpart is for the 32 bit world to have access to the lower
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* half only (with writes leaving the upper half untouched). It's
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* therefore useful to be able to pass TCG the offset of the least
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* significant half of a uint64_t struct member.
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*/
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#ifdef HOST_WORDS_BIGENDIAN
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#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
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#define offsetofhigh32(S, M) offsetof(S, M)
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#else
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#define offsetoflow32(S, M) offsetof(S, M)
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#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
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#endif
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/* Meanings of the ARMCPU object's four inbound GPIO lines */
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#define ARM_CPU_IRQ 0
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#define ARM_CPU_FIQ 1
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#define ARM_CPU_VIRQ 2
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#define ARM_CPU_VFIQ 3
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typedef void ARMWriteCPFunc(void *opaque, int cp_info,
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int srcreg, int operand, uint32_t value);
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typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
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int dstreg, int operand);
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struct arm_boot_info;
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#define NB_MMU_MODES 4
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/* We currently assume float and double are IEEE single and double
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precision respectively.
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Doing runtime conversions is tricky because VFP registers may contain
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integer values (eg. as the result of a FTOSI instruction).
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s<2n> maps to the least significant half of d<n>
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s<2n+1> maps to the most significant half of d<n>
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*/
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/* CPU state for each instance of a generic timer (in cp15 c14) */
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typedef struct ARMGenericTimer {
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uint64_t cval; /* Timer CompareValue register */
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uint64_t ctl; /* Timer Control register */
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} ARMGenericTimer;
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#define GTIMER_PHYS 0
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#define GTIMER_VIRT 1
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#define NUM_GTIMERS 2
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typedef struct CPUARMState {
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/* Regs for current mode. */
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uint32_t regs[16];
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/* 32/64 switch only happens when taking and returning from
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* exceptions so the overlap semantics are taken care of then
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* instead of having a complicated union.
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*/
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/* Regs for A64 mode. */
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uint64_t xregs[32];
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uint64_t pc;
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/* PSTATE isn't an architectural register for ARMv8. However, it is
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* convenient for us to assemble the underlying state into a 32 bit format
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* identical to the architectural format used for the SPSR. (This is also
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* what the Linux kernel's 'pstate' field in signal handlers and KVM's
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* 'pstate' register are.) Of the PSTATE bits:
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* NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
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* semantics as for AArch32, as described in the comments on each field)
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* nRW (also known as M[4]) is kept, inverted, in env->aarch64
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* DAIF (exception masks) are kept in env->daif
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* all other bits are stored in their correct places in env->pstate
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*/
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uint32_t pstate;
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uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
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/* Frequently accessed CPSR bits are stored separately for efficiency.
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This contains all the other bits. Use cpsr_{read,write} to access
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the whole CPSR. */
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uint32_t uncached_cpsr;
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uint32_t spsr;
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/* Banked registers. */
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uint64_t banked_spsr[8];
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uint32_t banked_r13[8];
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uint32_t banked_r14[8];
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/* These hold r8-r12. */
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uint32_t usr_regs[5];
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uint32_t fiq_regs[5];
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/* cpsr flag cache for faster execution */
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uint32_t CF; /* 0 or 1 */
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uint32_t VF; /* V is the bit 31. All other bits are undefined */
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uint32_t NF; /* N is bit 31. All other bits are undefined. */
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uint32_t ZF; /* Z set if zero. */
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uint32_t QF; /* 0 or 1 */
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uint32_t GE; /* cpsr[19:16] */
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uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
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uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
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uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
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uint64_t elr_el[4]; /* AArch64 exception link regs */
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uint64_t sp_el[4]; /* AArch64 banked stack pointers */
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/* System control coprocessor (cp15) */
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struct {
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uint32_t c0_cpuid;
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uint64_t c0_cssel; /* Cache size selection. */
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uint64_t c1_sys; /* System control register. */
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uint64_t c1_coproc; /* Coprocessor access register. */
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uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
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uint64_t sder; /* Secure debug enable register. */
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uint32_t nsacr; /* Non-secure access control register. */
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uint64_t ttbr0_el1; /* MMU translation table base 0. */
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uint64_t ttbr1_el1; /* MMU translation table base 1. */
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uint64_t c2_control; /* MMU translation table base control. */
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uint32_t c2_mask; /* MMU translation table base selection mask. */
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uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
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uint32_t c2_data; /* MPU data cachable bits. */
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uint32_t c2_insn; /* MPU instruction cachable bits. */
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uint32_t c3; /* MMU domain access control register
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MPU write buffer control. */
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uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
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uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
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uint64_t hcr_el2; /* Hypervisor configuration register */
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uint64_t scr_el3; /* Secure configuration register. */
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uint32_t ifsr_el2; /* Fault status registers. */
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uint64_t esr_el[4];
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uint32_t c6_region[8]; /* MPU base/size registers. */
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uint64_t far_el[4]; /* Fault address registers. */
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uint64_t par_el1; /* Translation result. */
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uint32_t c9_insn; /* Cache lockdown registers. */
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uint32_t c9_data;
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uint64_t c9_pmcr; /* performance monitor control register */
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uint64_t c9_pmcnten; /* perf monitor counter enables */
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uint32_t c9_pmovsr; /* perf monitor overflow status */
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uint32_t c9_pmxevtyper; /* perf monitor event type */
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uint32_t c9_pmuserenr; /* perf monitor user enable */
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uint32_t c9_pminten; /* perf monitor interrupt enables */
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uint64_t mair_el1;
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uint64_t vbar_el[4]; /* vector base address register */
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uint32_t c13_fcse; /* FCSE PID. */
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uint64_t contextidr_el1; /* Context ID. */
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uint64_t tpidr_el0; /* User RW Thread register. */
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uint64_t tpidrro_el0; /* User RO Thread register. */
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uint64_t tpidr_el1; /* Privileged Thread register. */
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uint64_t c14_cntfrq; /* Counter Frequency register */
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uint64_t c14_cntkctl; /* Timer Control register */
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ARMGenericTimer c14_timer[NUM_GTIMERS];
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uint32_t c15_cpar; /* XScale Coprocessor Access Register */
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uint32_t c15_ticonfig; /* TI925T configuration byte. */
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uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
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uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
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uint32_t c15_threadid; /* TI debugger thread-ID. */
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uint32_t c15_config_base_address; /* SCU base address. */
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uint32_t c15_diagnostic; /* diagnostic register */
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uint32_t c15_power_diagnostic;
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uint32_t c15_power_control; /* power control */
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uint64_t dbgbvr[16]; /* breakpoint value registers */
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uint64_t dbgbcr[16]; /* breakpoint control registers */
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uint64_t dbgwvr[16]; /* watchpoint value registers */
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uint64_t dbgwcr[16]; /* watchpoint control registers */
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uint64_t mdscr_el1;
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/* If the counter is enabled, this stores the last time the counter
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* was reset. Otherwise it stores the counter value
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*/
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uint64_t c15_ccnt;
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uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
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} cp15;
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struct {
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uint32_t other_sp;
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uint32_t vecbase;
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uint32_t basepri;
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uint32_t control;
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int current_sp;
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int exception;
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int pending_exception;
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} v7m;
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/* Information associated with an exception about to be taken:
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* code which raises an exception must set cs->exception_index and
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* the relevant parts of this structure; the cpu_do_interrupt function
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* will then set the guest-visible registers as part of the exception
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* entry process.
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*/
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struct {
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uint32_t syndrome; /* AArch64 format syndrome register */
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uint32_t fsr; /* AArch32 format fault status register info */
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uint64_t vaddress; /* virtual addr associated with exception, if any */
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/* If we implement EL2 we will also need to store information
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* about the intermediate physical address for stage 2 faults.
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*/
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} exception;
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/* Thumb-2 EE state. */
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uint32_t teecr;
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uint32_t teehbr;
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/* VFP coprocessor state. */
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struct {
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/* VFP/Neon register state. Note that the mapping between S, D and Q
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* views of the register bank differs between AArch64 and AArch32:
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* In AArch32:
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* Qn = regs[2n+1]:regs[2n]
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* Dn = regs[n]
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* Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
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* (and regs[32] to regs[63] are inaccessible)
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* In AArch64:
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* Qn = regs[2n+1]:regs[2n]
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* Dn = regs[2n]
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* Sn = regs[2n] bits 31..0
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* This corresponds to the architecturally defined mapping between
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* the two execution states, and means we do not need to explicitly
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* map these registers when changing states.
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*/
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float64 regs[64];
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uint32_t xregs[16];
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/* We store these fpcsr fields separately for convenience. */
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int vec_len;
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int vec_stride;
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/* scratch space when Tn are not sufficient. */
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uint32_t scratch[8];
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/* fp_status is the "normal" fp status. standard_fp_status retains
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* values corresponding to the ARM "Standard FPSCR Value", ie
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* default-NaN, flush-to-zero, round-to-nearest and is used by
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* any operations (generally Neon) which the architecture defines
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* as controlled by the standard FPSCR value rather than the FPSCR.
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*
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* To avoid having to transfer exception bits around, we simply
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* say that the FPSCR cumulative exception flags are the logical
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* OR of the flags in the two fp statuses. This relies on the
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* only thing which needs to read the exception flags being
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* an explicit FPSCR read.
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*/
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float_status fp_status;
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float_status standard_fp_status;
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} vfp;
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uint64_t exclusive_addr;
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uint64_t exclusive_val;
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uint64_t exclusive_high;
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#if defined(CONFIG_USER_ONLY)
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uint64_t exclusive_test;
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uint32_t exclusive_info;
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#endif
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/* iwMMXt coprocessor state. */
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struct {
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uint64_t regs[16];
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uint64_t val;
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uint32_t cregs[16];
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} iwmmxt;
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/* For mixed endian mode. */
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bool bswap_code;
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#if defined(CONFIG_USER_ONLY)
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/* For usermode syscall translation. */
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int eabi;
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#endif
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struct CPUBreakpoint *cpu_breakpoint[16];
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struct CPUWatchpoint *cpu_watchpoint[16];
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CPU_COMMON
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/* These fields after the common ones so they are preserved on reset. */
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/* Internal CPU feature flags. */
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uint64_t features;
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void *nvic;
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const struct arm_boot_info *boot_info;
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} CPUARMState;
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#include "cpu-qom.h"
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ARMCPU *cpu_arm_init(const char *cpu_model);
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int cpu_arm_exec(CPUARMState *s);
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uint32_t do_arm_semihosting(CPUARMState *env);
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static inline bool is_a64(CPUARMState *env)
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{
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return env->aarch64;
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}
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_arm_signal_handler(int host_signum, void *pinfo,
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void *puc);
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int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
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int mmu_idx);
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/**
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* pmccntr_sync
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* @env: CPUARMState
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*
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* Synchronises the counter in the PMCCNTR. This must always be called twice,
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* once before any action that might affect the timer and again afterwards.
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* The function is used to swap the state of the register if required.
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* This only happens when not in user mode (!CONFIG_USER_ONLY)
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*/
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void pmccntr_sync(CPUARMState *env);
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/* SCTLR bit meanings. Several bits have been reused in newer
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* versions of the architecture; in that case we define constants
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* for both old and new bit meanings. Code which tests against those
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* bits should probably check or otherwise arrange that the CPU
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* is the architectural version it expects.
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*/
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#define SCTLR_M (1U << 0)
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#define SCTLR_A (1U << 1)
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#define SCTLR_C (1U << 2)
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#define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
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#define SCTLR_SA (1U << 3)
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#define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
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#define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
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#define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
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#define SCTLR_CP15BEN (1U << 5) /* v7 onward */
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#define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
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#define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
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#define SCTLR_ITD (1U << 7) /* v8 onward */
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#define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
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#define SCTLR_SED (1U << 8) /* v8 onward */
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#define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
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#define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
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#define SCTLR_F (1U << 10) /* up to v6 */
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#define SCTLR_SW (1U << 10) /* v7 onward */
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#define SCTLR_Z (1U << 11)
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#define SCTLR_I (1U << 12)
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#define SCTLR_V (1U << 13)
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#define SCTLR_RR (1U << 14) /* up to v7 */
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#define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
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#define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
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#define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
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#define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
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#define SCTLR_nTWI (1U << 16) /* v8 onward */
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#define SCTLR_HA (1U << 17)
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#define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
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#define SCTLR_nTWE (1U << 18) /* v8 onward */
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#define SCTLR_WXN (1U << 19)
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#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
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#define SCTLR_UWXN (1U << 20) /* v7 onward */
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#define SCTLR_FI (1U << 21)
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#define SCTLR_U (1U << 22)
|
|
#define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
|
|
#define SCTLR_VE (1U << 24) /* up to v7 */
|
|
#define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
|
|
#define SCTLR_EE (1U << 25)
|
|
#define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
|
|
#define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
|
|
#define SCTLR_NMFI (1U << 27)
|
|
#define SCTLR_TRE (1U << 28)
|
|
#define SCTLR_AFE (1U << 29)
|
|
#define SCTLR_TE (1U << 30)
|
|
|
|
#define CPSR_M (0x1fU)
|
|
#define CPSR_T (1U << 5)
|
|
#define CPSR_F (1U << 6)
|
|
#define CPSR_I (1U << 7)
|
|
#define CPSR_A (1U << 8)
|
|
#define CPSR_E (1U << 9)
|
|
#define CPSR_IT_2_7 (0xfc00U)
|
|
#define CPSR_GE (0xfU << 16)
|
|
#define CPSR_IL (1U << 20)
|
|
/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
|
|
* an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
|
|
* env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
|
|
* where it is live state but not accessible to the AArch32 code.
|
|
*/
|
|
#define CPSR_RESERVED (0x7U << 21)
|
|
#define CPSR_J (1U << 24)
|
|
#define CPSR_IT_0_1 (3U << 25)
|
|
#define CPSR_Q (1U << 27)
|
|
#define CPSR_V (1U << 28)
|
|
#define CPSR_C (1U << 29)
|
|
#define CPSR_Z (1U << 30)
|
|
#define CPSR_N (1U << 31)
|
|
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
|
|
#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
|
|
|
|
#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
|
|
#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
|
|
| CPSR_NZCV)
|
|
/* Bits writable in user mode. */
|
|
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
|
|
/* Execution state bits. MRS read as zero, MSR writes ignored. */
|
|
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
|
|
/* Mask of bits which may be set by exception return copying them from SPSR */
|
|
#define CPSR_ERET_MASK (~CPSR_RESERVED)
|
|
|
|
#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
|
|
#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
|
|
#define TTBCR_PD0 (1U << 4)
|
|
#define TTBCR_PD1 (1U << 5)
|
|
#define TTBCR_EPD0 (1U << 7)
|
|
#define TTBCR_IRGN0 (3U << 8)
|
|
#define TTBCR_ORGN0 (3U << 10)
|
|
#define TTBCR_SH0 (3U << 12)
|
|
#define TTBCR_T1SZ (3U << 16)
|
|
#define TTBCR_A1 (1U << 22)
|
|
#define TTBCR_EPD1 (1U << 23)
|
|
#define TTBCR_IRGN1 (3U << 24)
|
|
#define TTBCR_ORGN1 (3U << 26)
|
|
#define TTBCR_SH1 (1U << 28)
|
|
#define TTBCR_EAE (1U << 31)
|
|
|
|
/* Bit definitions for ARMv8 SPSR (PSTATE) format.
|
|
* Only these are valid when in AArch64 mode; in
|
|
* AArch32 mode SPSRs are basically CPSR-format.
|
|
*/
|
|
#define PSTATE_SP (1U)
|
|
#define PSTATE_M (0xFU)
|
|
#define PSTATE_nRW (1U << 4)
|
|
#define PSTATE_F (1U << 6)
|
|
#define PSTATE_I (1U << 7)
|
|
#define PSTATE_A (1U << 8)
|
|
#define PSTATE_D (1U << 9)
|
|
#define PSTATE_IL (1U << 20)
|
|
#define PSTATE_SS (1U << 21)
|
|
#define PSTATE_V (1U << 28)
|
|
#define PSTATE_C (1U << 29)
|
|
#define PSTATE_Z (1U << 30)
|
|
#define PSTATE_N (1U << 31)
|
|
#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
|
|
#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
|
|
#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
|
|
/* Mode values for AArch64 */
|
|
#define PSTATE_MODE_EL3h 13
|
|
#define PSTATE_MODE_EL3t 12
|
|
#define PSTATE_MODE_EL2h 9
|
|
#define PSTATE_MODE_EL2t 8
|
|
#define PSTATE_MODE_EL1h 5
|
|
#define PSTATE_MODE_EL1t 4
|
|
#define PSTATE_MODE_EL0t 0
|
|
|
|
/* Map EL and handler into a PSTATE_MODE. */
|
|
static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
|
|
{
|
|
return (el << 2) | handler;
|
|
}
|
|
|
|
/* Return the current PSTATE value. For the moment we don't support 32<->64 bit
|
|
* interprocessing, so we don't attempt to sync with the cpsr state used by
|
|
* the 32 bit decoder.
|
|
*/
|
|
static inline uint32_t pstate_read(CPUARMState *env)
|
|
{
|
|
int ZF;
|
|
|
|
ZF = (env->ZF == 0);
|
|
return (env->NF & 0x80000000) | (ZF << 30)
|
|
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
|
|
| env->pstate | env->daif;
|
|
}
|
|
|
|
static inline void pstate_write(CPUARMState *env, uint32_t val)
|
|
{
|
|
env->ZF = (~val) & PSTATE_Z;
|
|
env->NF = val;
|
|
env->CF = (val >> 29) & 1;
|
|
env->VF = (val << 3) & 0x80000000;
|
|
env->daif = val & PSTATE_DAIF;
|
|
env->pstate = val & ~CACHED_PSTATE_BITS;
|
|
}
|
|
|
|
/* Return the current CPSR value. */
|
|
uint32_t cpsr_read(CPUARMState *env);
|
|
/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
|
|
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
|
|
|
|
/* Return the current xPSR value. */
|
|
static inline uint32_t xpsr_read(CPUARMState *env)
|
|
{
|
|
int ZF;
|
|
ZF = (env->ZF == 0);
|
|
return (env->NF & 0x80000000) | (ZF << 30)
|
|
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
|
|
| (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
|
|
| ((env->condexec_bits & 0xfc) << 8)
|
|
| env->v7m.exception;
|
|
}
|
|
|
|
/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
|
|
static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
|
|
{
|
|
if (mask & CPSR_NZCV) {
|
|
env->ZF = (~val) & CPSR_Z;
|
|
env->NF = val;
|
|
env->CF = (val >> 29) & 1;
|
|
env->VF = (val << 3) & 0x80000000;
|
|
}
|
|
if (mask & CPSR_Q)
|
|
env->QF = ((val & CPSR_Q) != 0);
|
|
if (mask & (1 << 24))
|
|
env->thumb = ((val & (1 << 24)) != 0);
|
|
if (mask & CPSR_IT_0_1) {
|
|
env->condexec_bits &= ~3;
|
|
env->condexec_bits |= (val >> 25) & 3;
|
|
}
|
|
if (mask & CPSR_IT_2_7) {
|
|
env->condexec_bits &= 3;
|
|
env->condexec_bits |= (val >> 8) & 0xfc;
|
|
}
|
|
if (mask & 0x1ff) {
|
|
env->v7m.exception = val & 0x1ff;
|
|
}
|
|
}
|
|
|
|
#define HCR_VM (1ULL << 0)
|
|
#define HCR_SWIO (1ULL << 1)
|
|
#define HCR_PTW (1ULL << 2)
|
|
#define HCR_FMO (1ULL << 3)
|
|
#define HCR_IMO (1ULL << 4)
|
|
#define HCR_AMO (1ULL << 5)
|
|
#define HCR_VF (1ULL << 6)
|
|
#define HCR_VI (1ULL << 7)
|
|
#define HCR_VSE (1ULL << 8)
|
|
#define HCR_FB (1ULL << 9)
|
|
#define HCR_BSU_MASK (3ULL << 10)
|
|
#define HCR_DC (1ULL << 12)
|
|
#define HCR_TWI (1ULL << 13)
|
|
#define HCR_TWE (1ULL << 14)
|
|
#define HCR_TID0 (1ULL << 15)
|
|
#define HCR_TID1 (1ULL << 16)
|
|
#define HCR_TID2 (1ULL << 17)
|
|
#define HCR_TID3 (1ULL << 18)
|
|
#define HCR_TSC (1ULL << 19)
|
|
#define HCR_TIDCP (1ULL << 20)
|
|
#define HCR_TACR (1ULL << 21)
|
|
#define HCR_TSW (1ULL << 22)
|
|
#define HCR_TPC (1ULL << 23)
|
|
#define HCR_TPU (1ULL << 24)
|
|
#define HCR_TTLB (1ULL << 25)
|
|
#define HCR_TVM (1ULL << 26)
|
|
#define HCR_TGE (1ULL << 27)
|
|
#define HCR_TDZ (1ULL << 28)
|
|
#define HCR_HCD (1ULL << 29)
|
|
#define HCR_TRVM (1ULL << 30)
|
|
#define HCR_RW (1ULL << 31)
|
|
#define HCR_CD (1ULL << 32)
|
|
#define HCR_ID (1ULL << 33)
|
|
#define HCR_MASK ((1ULL << 34) - 1)
|
|
|
|
#define SCR_NS (1U << 0)
|
|
#define SCR_IRQ (1U << 1)
|
|
#define SCR_FIQ (1U << 2)
|
|
#define SCR_EA (1U << 3)
|
|
#define SCR_FW (1U << 4)
|
|
#define SCR_AW (1U << 5)
|
|
#define SCR_NET (1U << 6)
|
|
#define SCR_SMD (1U << 7)
|
|
#define SCR_HCE (1U << 8)
|
|
#define SCR_SIF (1U << 9)
|
|
#define SCR_RW (1U << 10)
|
|
#define SCR_ST (1U << 11)
|
|
#define SCR_TWI (1U << 12)
|
|
#define SCR_TWE (1U << 13)
|
|
#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
|
|
#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
|
|
|
|
/* Return the current FPSCR value. */
|
|
uint32_t vfp_get_fpscr(CPUARMState *env);
|
|
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
|
|
|
|
/* For A64 the FPSCR is split into two logically distinct registers,
|
|
* FPCR and FPSR. However since they still use non-overlapping bits
|
|
* we store the underlying state in fpscr and just mask on read/write.
|
|
*/
|
|
#define FPSR_MASK 0xf800009f
|
|
#define FPCR_MASK 0x07f79f00
|
|
static inline uint32_t vfp_get_fpsr(CPUARMState *env)
|
|
{
|
|
return vfp_get_fpscr(env) & FPSR_MASK;
|
|
}
|
|
|
|
static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
|
|
{
|
|
uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
|
|
vfp_set_fpscr(env, new_fpscr);
|
|
}
|
|
|
|
static inline uint32_t vfp_get_fpcr(CPUARMState *env)
|
|
{
|
|
return vfp_get_fpscr(env) & FPCR_MASK;
|
|
}
|
|
|
|
static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
|
|
{
|
|
uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
|
|
vfp_set_fpscr(env, new_fpscr);
|
|
}
|
|
|
|
enum arm_cpu_mode {
|
|
ARM_CPU_MODE_USR = 0x10,
|
|
ARM_CPU_MODE_FIQ = 0x11,
|
|
ARM_CPU_MODE_IRQ = 0x12,
|
|
ARM_CPU_MODE_SVC = 0x13,
|
|
ARM_CPU_MODE_MON = 0x16,
|
|
ARM_CPU_MODE_ABT = 0x17,
|
|
ARM_CPU_MODE_HYP = 0x1a,
|
|
ARM_CPU_MODE_UND = 0x1b,
|
|
ARM_CPU_MODE_SYS = 0x1f
|
|
};
|
|
|
|
/* VFP system registers. */
|
|
#define ARM_VFP_FPSID 0
|
|
#define ARM_VFP_FPSCR 1
|
|
#define ARM_VFP_MVFR2 5
|
|
#define ARM_VFP_MVFR1 6
|
|
#define ARM_VFP_MVFR0 7
|
|
#define ARM_VFP_FPEXC 8
|
|
#define ARM_VFP_FPINST 9
|
|
#define ARM_VFP_FPINST2 10
|
|
|
|
/* iwMMXt coprocessor control registers. */
|
|
#define ARM_IWMMXT_wCID 0
|
|
#define ARM_IWMMXT_wCon 1
|
|
#define ARM_IWMMXT_wCSSF 2
|
|
#define ARM_IWMMXT_wCASF 3
|
|
#define ARM_IWMMXT_wCGR0 8
|
|
#define ARM_IWMMXT_wCGR1 9
|
|
#define ARM_IWMMXT_wCGR2 10
|
|
#define ARM_IWMMXT_wCGR3 11
|
|
|
|
/* If adding a feature bit which corresponds to a Linux ELF
|
|
* HWCAP bit, remember to update the feature-bit-to-hwcap
|
|
* mapping in linux-user/elfload.c:get_elf_hwcap().
|
|
*/
|
|
enum arm_features {
|
|
ARM_FEATURE_VFP,
|
|
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
|
|
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
|
|
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
|
|
ARM_FEATURE_V6,
|
|
ARM_FEATURE_V6K,
|
|
ARM_FEATURE_V7,
|
|
ARM_FEATURE_THUMB2,
|
|
ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
|
|
ARM_FEATURE_VFP3,
|
|
ARM_FEATURE_VFP_FP16,
|
|
ARM_FEATURE_NEON,
|
|
ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
|
|
ARM_FEATURE_M, /* Microcontroller profile. */
|
|
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
|
|
ARM_FEATURE_THUMB2EE,
|
|
ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
|
|
ARM_FEATURE_V4T,
|
|
ARM_FEATURE_V5,
|
|
ARM_FEATURE_STRONGARM,
|
|
ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
|
|
ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
|
|
ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
|
|
ARM_FEATURE_GENERIC_TIMER,
|
|
ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
|
|
ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
|
|
ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
|
|
ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
|
|
ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
|
|
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
|
|
ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
|
|
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
|
|
ARM_FEATURE_V8,
|
|
ARM_FEATURE_AARCH64, /* supports 64 bit mode */
|
|
ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
|
|
ARM_FEATURE_CBAR, /* has cp15 CBAR */
|
|
ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
|
|
ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
|
|
ARM_FEATURE_EL2, /* has EL2 Virtualization support */
|
|
ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
|
|
ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */
|
|
ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
|
|
ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
|
|
};
|
|
|
|
static inline int arm_feature(CPUARMState *env, int feature)
|
|
{
|
|
return (env->features & (1ULL << feature)) != 0;
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
/* Return true if exception levels below EL3 are in secure state,
|
|
* or would be following an exception return to that level.
|
|
* Unlike arm_is_secure() (which is always a question about the
|
|
* _current_ state of the CPU) this doesn't care about the current
|
|
* EL or mode.
|
|
*/
|
|
static inline bool arm_is_secure_below_el3(CPUARMState *env)
|
|
{
|
|
if (arm_feature(env, ARM_FEATURE_EL3)) {
|
|
return !(env->cp15.scr_el3 & SCR_NS);
|
|
} else {
|
|
/* If EL2 is not supported then the secure state is implementation
|
|
* defined, in which case QEMU defaults to non-secure.
|
|
*/
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/* Return true if the processor is in secure state */
|
|
static inline bool arm_is_secure(CPUARMState *env)
|
|
{
|
|
if (arm_feature(env, ARM_FEATURE_EL3)) {
|
|
if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
|
|
/* CPU currently in AArch64 state and EL3 */
|
|
return true;
|
|
} else if (!is_a64(env) &&
|
|
(env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
|
|
/* CPU currently in AArch32 state and monitor mode */
|
|
return true;
|
|
}
|
|
}
|
|
return arm_is_secure_below_el3(env);
|
|
}
|
|
|
|
#else
|
|
static inline bool arm_is_secure_below_el3(CPUARMState *env)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static inline bool arm_is_secure(CPUARMState *env)
|
|
{
|
|
return false;
|
|
}
|
|
#endif
|
|
|
|
/* Return true if the specified exception level is running in AArch64 state. */
|
|
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
|
|
{
|
|
/* We don't currently support EL2, and this isn't valid for EL0
|
|
* (if we're in EL0, is_a64() is what you want, and if we're not in EL0
|
|
* then the state of EL0 isn't well defined.)
|
|
*/
|
|
assert(el == 1 || el == 3);
|
|
|
|
/* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
|
|
* is a QEMU-imposed simplification which we may wish to change later.
|
|
* If we in future support EL2 and/or EL3, then the state of lower
|
|
* exception levels is controlled by the HCR.RW and SCR.RW bits.
|
|
*/
|
|
return arm_feature(env, ARM_FEATURE_AARCH64);
|
|
}
|
|
|
|
/* Function for determing whether guest cp register reads and writes should
|
|
* access the secure or non-secure bank of a cp register. When EL3 is
|
|
* operating in AArch32 state, the NS-bit determines whether the secure
|
|
* instance of a cp register should be used. When EL3 is AArch64 (or if
|
|
* it doesn't exist at all) then there is no register banking, and all
|
|
* accesses are to the non-secure version.
|
|
*/
|
|
static inline bool access_secure_reg(CPUARMState *env)
|
|
{
|
|
bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
|
|
!arm_el_is_aa64(env, 3) &&
|
|
!(env->cp15.scr_el3 & SCR_NS));
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Macros for accessing a specified CP register bank */
|
|
#define A32_BANKED_REG_GET(_env, _regname, _secure) \
|
|
((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
|
|
|
|
#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
|
|
do { \
|
|
if (_secure) { \
|
|
(_env)->cp15._regname##_s = (_val); \
|
|
} else { \
|
|
(_env)->cp15._regname##_ns = (_val); \
|
|
} \
|
|
} while (0)
|
|
|
|
/* Macros for automatically accessing a specific CP register bank depending on
|
|
* the current secure state of the system. These macros are not intended for
|
|
* supporting instruction translation reads/writes as these are dependent
|
|
* solely on the SCR.NS bit and not the mode.
|
|
*/
|
|
#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
|
|
A32_BANKED_REG_GET((_env), _regname, \
|
|
((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))))
|
|
|
|
#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
|
|
A32_BANKED_REG_SET((_env), _regname, \
|
|
((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \
|
|
(_val))
|
|
|
|
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
|
unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);
|
|
|
|
/* Interface between CPU and Interrupt controller. */
|
|
void armv7m_nvic_set_pending(void *opaque, int irq);
|
|
int armv7m_nvic_acknowledge_irq(void *opaque);
|
|
void armv7m_nvic_complete_irq(void *opaque, int irq);
|
|
|
|
/* Interface for defining coprocessor registers.
|
|
* Registers are defined in tables of arm_cp_reginfo structs
|
|
* which are passed to define_arm_cp_regs().
|
|
*/
|
|
|
|
/* When looking up a coprocessor register we look for it
|
|
* via an integer which encodes all of:
|
|
* coprocessor number
|
|
* Crn, Crm, opc1, opc2 fields
|
|
* 32 or 64 bit register (ie is it accessed via MRC/MCR
|
|
* or via MRRC/MCRR?)
|
|
* non-secure/secure bank (AArch32 only)
|
|
* We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
|
|
* (In this case crn and opc2 should be zero.)
|
|
* For AArch64, there is no 32/64 bit size distinction;
|
|
* instead all registers have a 2 bit op0, 3 bit op1 and op2,
|
|
* and 4 bit CRn and CRm. The encoding patterns are chosen
|
|
* to be easy to convert to and from the KVM encodings, and also
|
|
* so that the hashtable can contain both AArch32 and AArch64
|
|
* registers (to allow for interprocessing where we might run
|
|
* 32 bit code on a 64 bit core).
|
|
*/
|
|
/* This bit is private to our hashtable cpreg; in KVM register
|
|
* IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
|
|
* in the upper bits of the 64 bit ID.
|
|
*/
|
|
#define CP_REG_AA64_SHIFT 28
|
|
#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
|
|
|
|
/* To enable banking of coprocessor registers depending on ns-bit we
|
|
* add a bit to distinguish between secure and non-secure cpregs in the
|
|
* hashtable.
|
|
*/
|
|
#define CP_REG_NS_SHIFT 29
|
|
#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
|
|
|
|
#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
|
|
((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
|
|
((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
|
|
|
|
#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
|
|
(CP_REG_AA64_MASK | \
|
|
((cp) << CP_REG_ARM_COPROC_SHIFT) | \
|
|
((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
|
|
((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
|
|
((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
|
|
((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
|
|
((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
|
|
|
|
/* Convert a full 64 bit KVM register ID to the truncated 32 bit
|
|
* version used as a key for the coprocessor register hashtable
|
|
*/
|
|
static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
|
|
{
|
|
uint32_t cpregid = kvmid;
|
|
if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
|
|
cpregid |= CP_REG_AA64_MASK;
|
|
} else {
|
|
if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
|
|
cpregid |= (1 << 15);
|
|
}
|
|
|
|
/* KVM is always non-secure so add the NS flag on AArch32 register
|
|
* entries.
|
|
*/
|
|
cpregid |= 1 << CP_REG_NS_SHIFT;
|
|
}
|
|
return cpregid;
|
|
}
|
|
|
|
/* Convert a truncated 32 bit hashtable key into the full
|
|
* 64 bit KVM register ID.
|
|
*/
|
|
static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
|
|
{
|
|
uint64_t kvmid;
|
|
|
|
if (cpregid & CP_REG_AA64_MASK) {
|
|
kvmid = cpregid & ~CP_REG_AA64_MASK;
|
|
kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
|
|
} else {
|
|
kvmid = cpregid & ~(1 << 15);
|
|
if (cpregid & (1 << 15)) {
|
|
kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
|
|
} else {
|
|
kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
|
|
}
|
|
}
|
|
return kvmid;
|
|
}
|
|
|
|
/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
|
|
* special-behaviour cp reg and bits [15..8] indicate what behaviour
|
|
* it has. Otherwise it is a simple cp reg, where CONST indicates that
|
|
* TCG can assume the value to be constant (ie load at translate time)
|
|
* and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
|
|
* indicates that the TB should not be ended after a write to this register
|
|
* (the default is that the TB ends after cp writes). OVERRIDE permits
|
|
* a register definition to override a previous definition for the
|
|
* same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
|
|
* old must have the OVERRIDE bit set.
|
|
* NO_MIGRATE indicates that this register should be ignored for migration;
|
|
* (eg because any state is accessed via some other coprocessor register).
|
|
* IO indicates that this register does I/O and therefore its accesses
|
|
* need to be surrounded by gen_io_start()/gen_io_end(). In particular,
|
|
* registers which implement clocks or timers require this.
|
|
*/
|
|
#define ARM_CP_SPECIAL 1
|
|
#define ARM_CP_CONST 2
|
|
#define ARM_CP_64BIT 4
|
|
#define ARM_CP_SUPPRESS_TB_END 8
|
|
#define ARM_CP_OVERRIDE 16
|
|
#define ARM_CP_NO_MIGRATE 32
|
|
#define ARM_CP_IO 64
|
|
#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
|
|
#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
|
|
#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
|
|
#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
|
|
#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
|
|
#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
|
|
/* Used only as a terminator for ARMCPRegInfo lists */
|
|
#define ARM_CP_SENTINEL 0xffff
|
|
/* Mask of only the flag bits in a type field */
|
|
#define ARM_CP_FLAG_MASK 0x7f
|
|
|
|
/* Valid values for ARMCPRegInfo state field, indicating which of
|
|
* the AArch32 and AArch64 execution states this register is visible in.
|
|
* If the reginfo doesn't explicitly specify then it is AArch32 only.
|
|
* If the reginfo is declared to be visible in both states then a second
|
|
* reginfo is synthesised for the AArch32 view of the AArch64 register,
|
|
* such that the AArch32 view is the lower 32 bits of the AArch64 one.
|
|
* Note that we rely on the values of these enums as we iterate through
|
|
* the various states in some places.
|
|
*/
|
|
enum {
|
|
ARM_CP_STATE_AA32 = 0,
|
|
ARM_CP_STATE_AA64 = 1,
|
|
ARM_CP_STATE_BOTH = 2,
|
|
};
|
|
|
|
/* ARM CP register secure state flags. These flags identify security state
|
|
* attributes for a given CP register entry.
|
|
* The existence of both or neither secure and non-secure flags indicates that
|
|
* the register has both a secure and non-secure hash entry. A single one of
|
|
* these flags causes the register to only be hashed for the specified
|
|
* security state.
|
|
* Although definitions may have any combination of the S/NS bits, each
|
|
* registered entry will only have one to identify whether the entry is secure
|
|
* or non-secure.
|
|
*/
|
|
enum {
|
|
ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
|
|
ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
|
|
};
|
|
|
|
/* Return true if cptype is a valid type field. This is used to try to
|
|
* catch errors where the sentinel has been accidentally left off the end
|
|
* of a list of registers.
|
|
*/
|
|
static inline bool cptype_valid(int cptype)
|
|
{
|
|
return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
|
|
|| ((cptype & ARM_CP_SPECIAL) &&
|
|
((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
|
|
}
|
|
|
|
/* Access rights:
|
|
* We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
|
|
* defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
|
|
* PL2 (hyp). The other level which has Read and Write bits is Secure PL1
|
|
* (ie any of the privileged modes in Secure state, or Monitor mode).
|
|
* If a register is accessible in one privilege level it's always accessible
|
|
* in higher privilege levels too. Since "Secure PL1" also follows this rule
|
|
* (ie anything visible in PL2 is visible in S-PL1, some things are only
|
|
* visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
|
|
* terminology a little and call this PL3.
|
|
* In AArch64 things are somewhat simpler as the PLx bits line up exactly
|
|
* with the ELx exception levels.
|
|
*
|
|
* If access permissions for a register are more complex than can be
|
|
* described with these bits, then use a laxer set of restrictions, and
|
|
* do the more restrictive/complex check inside a helper function.
|
|
*/
|
|
#define PL3_R 0x80
|
|
#define PL3_W 0x40
|
|
#define PL2_R (0x20 | PL3_R)
|
|
#define PL2_W (0x10 | PL3_W)
|
|
#define PL1_R (0x08 | PL2_R)
|
|
#define PL1_W (0x04 | PL2_W)
|
|
#define PL0_R (0x02 | PL1_R)
|
|
#define PL0_W (0x01 | PL1_W)
|
|
|
|
#define PL3_RW (PL3_R | PL3_W)
|
|
#define PL2_RW (PL2_R | PL2_W)
|
|
#define PL1_RW (PL1_R | PL1_W)
|
|
#define PL0_RW (PL0_R | PL0_W)
|
|
|
|
/* Return the current Exception Level (as per ARMv8; note that this differs
|
|
* from the ARMv7 Privilege Level).
|
|
*/
|
|
static inline int arm_current_el(CPUARMState *env)
|
|
{
|
|
if (is_a64(env)) {
|
|
return extract32(env->pstate, 2, 2);
|
|
}
|
|
|
|
switch (env->uncached_cpsr & 0x1f) {
|
|
case ARM_CPU_MODE_USR:
|
|
return 0;
|
|
case ARM_CPU_MODE_HYP:
|
|
return 2;
|
|
case ARM_CPU_MODE_MON:
|
|
return 3;
|
|
default:
|
|
if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
|
|
/* If EL3 is 32-bit then all secure privileged modes run in
|
|
* EL3
|
|
*/
|
|
return 3;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
typedef struct ARMCPRegInfo ARMCPRegInfo;
|
|
|
|
typedef enum CPAccessResult {
|
|
/* Access is permitted */
|
|
CP_ACCESS_OK = 0,
|
|
/* Access fails due to a configurable trap or enable which would
|
|
* result in a categorized exception syndrome giving information about
|
|
* the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
|
|
* 0xc or 0x18).
|
|
*/
|
|
CP_ACCESS_TRAP = 1,
|
|
/* Access fails and results in an exception syndrome 0x0 ("uncategorized").
|
|
* Note that this is not a catch-all case -- the set of cases which may
|
|
* result in this failure is specifically defined by the architecture.
|
|
*/
|
|
CP_ACCESS_TRAP_UNCATEGORIZED = 2,
|
|
} CPAccessResult;
|
|
|
|
/* Access functions for coprocessor registers. These cannot fail and
|
|
* may not raise exceptions.
|
|
*/
|
|
typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
|
|
typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
|
|
uint64_t value);
|
|
/* Access permission check functions for coprocessor registers. */
|
|
typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque);
|
|
/* Hook function for register reset */
|
|
typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
|
|
|
|
#define CP_ANY 0xff
|
|
|
|
/* Definition of an ARM coprocessor register */
|
|
struct ARMCPRegInfo {
|
|
/* Name of register (useful mainly for debugging, need not be unique) */
|
|
const char *name;
|
|
/* Location of register: coprocessor number and (crn,crm,opc1,opc2)
|
|
* tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
|
|
* 'wildcard' field -- any value of that field in the MRC/MCR insn
|
|
* will be decoded to this register. The register read and write
|
|
* callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
|
|
* used by the program, so it is possible to register a wildcard and
|
|
* then behave differently on read/write if necessary.
|
|
* For 64 bit registers, only crm and opc1 are relevant; crn and opc2
|
|
* must both be zero.
|
|
* For AArch64-visible registers, opc0 is also used.
|
|
* Since there are no "coprocessors" in AArch64, cp is purely used as a
|
|
* way to distinguish (for KVM's benefit) guest-visible system registers
|
|
* from demuxed ones provided to preserve the "no side effects on
|
|
* KVM register read/write from QEMU" semantics. cp==0x13 is guest
|
|
* visible (to match KVM's encoding); cp==0 will be converted to
|
|
* cp==0x13 when the ARMCPRegInfo is registered, for convenience.
|
|
*/
|
|
uint8_t cp;
|
|
uint8_t crn;
|
|
uint8_t crm;
|
|
uint8_t opc0;
|
|
uint8_t opc1;
|
|
uint8_t opc2;
|
|
/* Execution state in which this register is visible: ARM_CP_STATE_* */
|
|
int state;
|
|
/* Register type: ARM_CP_* bits/values */
|
|
int type;
|
|
/* Access rights: PL*_[RW] */
|
|
int access;
|
|
/* Security state: ARM_CP_SECSTATE_* bits/values */
|
|
int secure;
|
|
/* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
|
|
* this register was defined: can be used to hand data through to the
|
|
* register read/write functions, since they are passed the ARMCPRegInfo*.
|
|
*/
|
|
void *opaque;
|
|
/* Value of this register, if it is ARM_CP_CONST. Otherwise, if
|
|
* fieldoffset is non-zero, the reset value of the register.
|
|
*/
|
|
uint64_t resetvalue;
|
|
/* Offset of the field in CPUARMState for this register.
|
|
*
|
|
* This is not needed if either:
|
|
* 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
|
|
* 2. both readfn and writefn are specified
|
|
*/
|
|
ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
|
|
|
|
/* Offsets of the secure and non-secure fields in CPUARMState for the
|
|
* register if it is banked. These fields are only used during the static
|
|
* registration of a register. During hashing the bank associated
|
|
* with a given security state is copied to fieldoffset which is used from
|
|
* there on out.
|
|
*
|
|
* It is expected that register definitions use either fieldoffset or
|
|
* bank_fieldoffsets in the definition but not both. It is also expected
|
|
* that both bank offsets are set when defining a banked register. This
|
|
* use indicates that a register is banked.
|
|
*/
|
|
ptrdiff_t bank_fieldoffsets[2];
|
|
|
|
/* Function for making any access checks for this register in addition to
|
|
* those specified by the 'access' permissions bits. If NULL, no extra
|
|
* checks required. The access check is performed at runtime, not at
|
|
* translate time.
|
|
*/
|
|
CPAccessFn *accessfn;
|
|
/* Function for handling reads of this register. If NULL, then reads
|
|
* will be done by loading from the offset into CPUARMState specified
|
|
* by fieldoffset.
|
|
*/
|
|
CPReadFn *readfn;
|
|
/* Function for handling writes of this register. If NULL, then writes
|
|
* will be done by writing to the offset into CPUARMState specified
|
|
* by fieldoffset.
|
|
*/
|
|
CPWriteFn *writefn;
|
|
/* Function for doing a "raw" read; used when we need to copy
|
|
* coprocessor state to the kernel for KVM or out for
|
|
* migration. This only needs to be provided if there is also a
|
|
* readfn and it has side effects (for instance clear-on-read bits).
|
|
*/
|
|
CPReadFn *raw_readfn;
|
|
/* Function for doing a "raw" write; used when we need to copy KVM
|
|
* kernel coprocessor state into userspace, or for inbound
|
|
* migration. This only needs to be provided if there is also a
|
|
* writefn and it masks out "unwritable" bits or has write-one-to-clear
|
|
* or similar behaviour.
|
|
*/
|
|
CPWriteFn *raw_writefn;
|
|
/* Function for resetting the register. If NULL, then reset will be done
|
|
* by writing resetvalue to the field specified in fieldoffset. If
|
|
* fieldoffset is 0 then no reset will be done.
|
|
*/
|
|
CPResetFn *resetfn;
|
|
};
|
|
|
|
/* Macros which are lvalues for the field in CPUARMState for the
|
|
* ARMCPRegInfo *ri.
|
|
*/
|
|
#define CPREG_FIELD32(env, ri) \
|
|
(*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
|
|
#define CPREG_FIELD64(env, ri) \
|
|
(*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
|
|
|
|
#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
|
|
|
|
void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
|
|
const ARMCPRegInfo *regs, void *opaque);
|
|
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
|
|
const ARMCPRegInfo *regs, void *opaque);
|
|
static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
|
|
{
|
|
define_arm_cp_regs_with_opaque(cpu, regs, 0);
|
|
}
|
|
static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
|
|
{
|
|
define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
|
|
}
|
|
const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
|
|
|
|
/* CPWriteFn that can be used to implement writes-ignored behaviour */
|
|
void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
uint64_t value);
|
|
/* CPReadFn that can be used for read-as-zero behaviour */
|
|
uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
|
|
|
|
/* CPResetFn that does nothing, for use if no reset is required even
|
|
* if fieldoffset is non zero.
|
|
*/
|
|
void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
|
|
|
|
/* Return true if this reginfo struct's field in the cpu state struct
|
|
* is 64 bits wide.
|
|
*/
|
|
static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
|
|
{
|
|
return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
|
|
}
|
|
|
|
static inline bool cp_access_ok(int current_el,
|
|
const ARMCPRegInfo *ri, int isread)
|
|
{
|
|
return (ri->access >> ((current_el * 2) + isread)) & 1;
|
|
}
|
|
|
|
/**
|
|
* write_list_to_cpustate
|
|
* @cpu: ARMCPU
|
|
*
|
|
* For each register listed in the ARMCPU cpreg_indexes list, write
|
|
* its value from the cpreg_values list into the ARMCPUState structure.
|
|
* This updates TCG's working data structures from KVM data or
|
|
* from incoming migration state.
|
|
*
|
|
* Returns: true if all register values were updated correctly,
|
|
* false if some register was unknown or could not be written.
|
|
* Note that we do not stop early on failure -- we will attempt
|
|
* writing all registers in the list.
|
|
*/
|
|
bool write_list_to_cpustate(ARMCPU *cpu);
|
|
|
|
/**
|
|
* write_cpustate_to_list:
|
|
* @cpu: ARMCPU
|
|
*
|
|
* For each register listed in the ARMCPU cpreg_indexes list, write
|
|
* its value from the ARMCPUState structure into the cpreg_values list.
|
|
* This is used to copy info from TCG's working data structures into
|
|
* KVM or for outbound migration.
|
|
*
|
|
* Returns: true if all register values were read correctly,
|
|
* false if some register was unknown or could not be read.
|
|
* Note that we do not stop early on failure -- we will attempt
|
|
* reading all registers in the list.
|
|
*/
|
|
bool write_cpustate_to_list(ARMCPU *cpu);
|
|
|
|
/* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
|
|
Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
|
|
conventional cores (ie. Application or Realtime profile). */
|
|
|
|
#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
|
|
|
|
#define ARM_CPUID_TI915T 0x54029152
|
|
#define ARM_CPUID_TI925T 0x54029252
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
#define TARGET_PAGE_BITS 12
|
|
#else
|
|
/* The ARM MMU allows 1k pages. */
|
|
/* ??? Linux doesn't actually use these, and they're deprecated in recent
|
|
architecture revisions. Maybe a configure option to disable them. */
|
|
#define TARGET_PAGE_BITS 10
|
|
#endif
|
|
|
|
#if defined(TARGET_AARCH64)
|
|
# define TARGET_PHYS_ADDR_SPACE_BITS 48
|
|
# define TARGET_VIRT_ADDR_SPACE_BITS 64
|
|
#else
|
|
# define TARGET_PHYS_ADDR_SPACE_BITS 40
|
|
# define TARGET_VIRT_ADDR_SPACE_BITS 32
|
|
#endif
|
|
|
|
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
|
|
{
|
|
CPUARMState *env = cs->env_ptr;
|
|
unsigned int cur_el = arm_current_el(env);
|
|
unsigned int target_el = arm_excp_target_el(cs, excp_idx);
|
|
bool secure = arm_is_secure(env);
|
|
uint32_t scr;
|
|
uint32_t hcr;
|
|
bool pstate_unmasked;
|
|
int8_t unmasked = 0;
|
|
|
|
/* Don't take exceptions if they target a lower EL.
|
|
* This check should catch any exceptions that would not be taken but left
|
|
* pending.
|
|
*/
|
|
if (cur_el > target_el) {
|
|
return false;
|
|
}
|
|
|
|
switch (excp_idx) {
|
|
case EXCP_FIQ:
|
|
/* If FIQs are routed to EL3 or EL2 then there are cases where we
|
|
* override the CPSR.F in determining if the exception is masked or
|
|
* not. If neither of these are set then we fall back to the CPSR.F
|
|
* setting otherwise we further assess the state below.
|
|
*/
|
|
hcr = (env->cp15.hcr_el2 & HCR_FMO);
|
|
scr = (env->cp15.scr_el3 & SCR_FIQ);
|
|
|
|
/* When EL3 is 32-bit, the SCR.FW bit controls whether the CPSR.F bit
|
|
* masks FIQ interrupts when taken in non-secure state. If SCR.FW is
|
|
* set then FIQs can be masked by CPSR.F when non-secure but only
|
|
* when FIQs are only routed to EL3.
|
|
*/
|
|
scr &= !((env->cp15.scr_el3 & SCR_FW) && !hcr);
|
|
pstate_unmasked = !(env->daif & PSTATE_F);
|
|
break;
|
|
|
|
case EXCP_IRQ:
|
|
/* When EL3 execution state is 32-bit, if HCR.IMO is set then we may
|
|
* override the CPSR.I masking when in non-secure state. The SCR.IRQ
|
|
* setting has already been taken into consideration when setting the
|
|
* target EL, so it does not have a further affect here.
|
|
*/
|
|
hcr = (env->cp15.hcr_el2 & HCR_IMO);
|
|
scr = false;
|
|
pstate_unmasked = !(env->daif & PSTATE_I);
|
|
break;
|
|
|
|
case EXCP_VFIQ:
|
|
if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
|
|
/* VFIQs are only taken when hypervized and non-secure. */
|
|
return false;
|
|
}
|
|
return !(env->daif & PSTATE_F);
|
|
case EXCP_VIRQ:
|
|
if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
|
|
/* VIRQs are only taken when hypervized and non-secure. */
|
|
return false;
|
|
}
|
|
return !(env->daif & PSTATE_I);
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
/* Use the target EL, current execution state and SCR/HCR settings to
|
|
* determine whether the corresponding CPSR bit is used to mask the
|
|
* interrupt.
|
|
*/
|
|
if ((target_el > cur_el) && (target_el != 1)) {
|
|
if (arm_el_is_aa64(env, 3) || ((scr || hcr) && (!secure))) {
|
|
unmasked = 1;
|
|
}
|
|
}
|
|
|
|
/* The PSTATE bits only mask the interrupt if we have not overriden the
|
|
* ability above.
|
|
*/
|
|
return unmasked || pstate_unmasked;
|
|
}
|
|
|
|
static inline CPUARMState *cpu_init(const char *cpu_model)
|
|
{
|
|
ARMCPU *cpu = cpu_arm_init(cpu_model);
|
|
if (cpu) {
|
|
return &cpu->env;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
#define cpu_exec cpu_arm_exec
|
|
#define cpu_gen_code cpu_arm_gen_code
|
|
#define cpu_signal_handler cpu_arm_signal_handler
|
|
#define cpu_list arm_cpu_list
|
|
|
|
/* MMU modes definitions */
|
|
#define MMU_MODE0_SUFFIX _user
|
|
#define MMU_MODE1_SUFFIX _kernel
|
|
#define MMU_USER_IDX 0
|
|
static inline int cpu_mmu_index (CPUARMState *env)
|
|
{
|
|
return arm_current_el(env);
|
|
}
|
|
|
|
/* Return the Exception Level targeted by debug exceptions;
|
|
* currently always EL1 since we don't implement EL2 or EL3.
|
|
*/
|
|
static inline int arm_debug_target_el(CPUARMState *env)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
|
|
{
|
|
if (arm_current_el(env) == arm_debug_target_el(env)) {
|
|
if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
|
|
|| (env->daif & PSTATE_D)) {
|
|
return false;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
|
|
{
|
|
if (arm_current_el(env) == 0 && arm_el_is_aa64(env, 1)) {
|
|
return aa64_generate_debug_exceptions(env);
|
|
}
|
|
return arm_current_el(env) != 2;
|
|
}
|
|
|
|
/* Return true if debugging exceptions are currently enabled.
|
|
* This corresponds to what in ARM ARM pseudocode would be
|
|
* if UsingAArch32() then
|
|
* return AArch32.GenerateDebugExceptions()
|
|
* else
|
|
* return AArch64.GenerateDebugExceptions()
|
|
* We choose to push the if() down into this function for clarity,
|
|
* since the pseudocode has it at all callsites except for the one in
|
|
* CheckSoftwareStep(), where it is elided because both branches would
|
|
* always return the same value.
|
|
*
|
|
* Parts of the pseudocode relating to EL2 and EL3 are omitted because we
|
|
* don't yet implement those exception levels or their associated trap bits.
|
|
*/
|
|
static inline bool arm_generate_debug_exceptions(CPUARMState *env)
|
|
{
|
|
if (env->aarch64) {
|
|
return aa64_generate_debug_exceptions(env);
|
|
} else {
|
|
return aa32_generate_debug_exceptions(env);
|
|
}
|
|
}
|
|
|
|
/* Is single-stepping active? (Note that the "is EL_D AArch64?" check
|
|
* implicitly means this always returns false in pre-v8 CPUs.)
|
|
*/
|
|
static inline bool arm_singlestep_active(CPUARMState *env)
|
|
{
|
|
return extract32(env->cp15.mdscr_el1, 0, 1)
|
|
&& arm_el_is_aa64(env, arm_debug_target_el(env))
|
|
&& arm_generate_debug_exceptions(env);
|
|
}
|
|
|
|
#include "exec/cpu-all.h"
|
|
|
|
/* Bit usage in the TB flags field: bit 31 indicates whether we are
|
|
* in 32 or 64 bit mode. The meaning of the other bits depends on that.
|
|
*/
|
|
#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
|
|
#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
|
|
|
|
/* Bit usage when in AArch32 state: */
|
|
#define ARM_TBFLAG_THUMB_SHIFT 0
|
|
#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
|
|
#define ARM_TBFLAG_VECLEN_SHIFT 1
|
|
#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
|
|
#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
|
|
#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
|
|
#define ARM_TBFLAG_PRIV_SHIFT 6
|
|
#define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT)
|
|
#define ARM_TBFLAG_VFPEN_SHIFT 7
|
|
#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
|
|
#define ARM_TBFLAG_CONDEXEC_SHIFT 8
|
|
#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
|
|
#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
|
|
#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
|
|
#define ARM_TBFLAG_CPACR_FPEN_SHIFT 17
|
|
#define ARM_TBFLAG_CPACR_FPEN_MASK (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT)
|
|
#define ARM_TBFLAG_SS_ACTIVE_SHIFT 18
|
|
#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
|
|
#define ARM_TBFLAG_PSTATE_SS_SHIFT 19
|
|
#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
|
|
/* We store the bottom two bits of the CPAR as TB flags and handle
|
|
* checks on the other bits at runtime
|
|
*/
|
|
#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20
|
|
#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
|
|
/* Indicates whether cp register reads and writes by guest code should access
|
|
* the secure or nonsecure bank of banked registers; note that this is not
|
|
* the same thing as the current security state of the processor!
|
|
*/
|
|
#define ARM_TBFLAG_NS_SHIFT 22
|
|
#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
|
|
|
|
/* Bit usage when in AArch64 state */
|
|
#define ARM_TBFLAG_AA64_EL_SHIFT 0
|
|
#define ARM_TBFLAG_AA64_EL_MASK (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
|
|
#define ARM_TBFLAG_AA64_FPEN_SHIFT 2
|
|
#define ARM_TBFLAG_AA64_FPEN_MASK (1 << ARM_TBFLAG_AA64_FPEN_SHIFT)
|
|
#define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3
|
|
#define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 << ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
|
|
#define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 4
|
|
#define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 << ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
|
|
|
|
/* some convenience accessor macros */
|
|
#define ARM_TBFLAG_AARCH64_STATE(F) \
|
|
(((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
|
|
#define ARM_TBFLAG_THUMB(F) \
|
|
(((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
|
|
#define ARM_TBFLAG_VECLEN(F) \
|
|
(((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
|
|
#define ARM_TBFLAG_VECSTRIDE(F) \
|
|
(((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
|
|
#define ARM_TBFLAG_PRIV(F) \
|
|
(((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
|
|
#define ARM_TBFLAG_VFPEN(F) \
|
|
(((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
|
|
#define ARM_TBFLAG_CONDEXEC(F) \
|
|
(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
|
|
#define ARM_TBFLAG_BSWAP_CODE(F) \
|
|
(((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
|
|
#define ARM_TBFLAG_CPACR_FPEN(F) \
|
|
(((F) & ARM_TBFLAG_CPACR_FPEN_MASK) >> ARM_TBFLAG_CPACR_FPEN_SHIFT)
|
|
#define ARM_TBFLAG_SS_ACTIVE(F) \
|
|
(((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
|
|
#define ARM_TBFLAG_PSTATE_SS(F) \
|
|
(((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
|
|
#define ARM_TBFLAG_XSCALE_CPAR(F) \
|
|
(((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
|
|
#define ARM_TBFLAG_AA64_EL(F) \
|
|
(((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
|
|
#define ARM_TBFLAG_AA64_FPEN(F) \
|
|
(((F) & ARM_TBFLAG_AA64_FPEN_MASK) >> ARM_TBFLAG_AA64_FPEN_SHIFT)
|
|
#define ARM_TBFLAG_AA64_SS_ACTIVE(F) \
|
|
(((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
|
|
#define ARM_TBFLAG_AA64_PSTATE_SS(F) \
|
|
(((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
|
|
#define ARM_TBFLAG_NS(F) \
|
|
(((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
|
|
|
|
static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
|
|
target_ulong *cs_base, int *flags)
|
|
{
|
|
int fpen;
|
|
|
|
if (arm_feature(env, ARM_FEATURE_V6)) {
|
|
fpen = extract32(env->cp15.c1_coproc, 20, 2);
|
|
} else {
|
|
/* CPACR doesn't exist before v6, so VFP is always accessible */
|
|
fpen = 3;
|
|
}
|
|
|
|
if (is_a64(env)) {
|
|
*pc = env->pc;
|
|
*flags = ARM_TBFLAG_AARCH64_STATE_MASK
|
|
| (arm_current_el(env) << ARM_TBFLAG_AA64_EL_SHIFT);
|
|
if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) {
|
|
*flags |= ARM_TBFLAG_AA64_FPEN_MASK;
|
|
}
|
|
/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
|
|
* states defined in the ARM ARM for software singlestep:
|
|
* SS_ACTIVE PSTATE.SS State
|
|
* 0 x Inactive (the TB flag for SS is always 0)
|
|
* 1 0 Active-pending
|
|
* 1 1 Active-not-pending
|
|
*/
|
|
if (arm_singlestep_active(env)) {
|
|
*flags |= ARM_TBFLAG_AA64_SS_ACTIVE_MASK;
|
|
if (env->pstate & PSTATE_SS) {
|
|
*flags |= ARM_TBFLAG_AA64_PSTATE_SS_MASK;
|
|
}
|
|
}
|
|
} else {
|
|
int privmode;
|
|
*pc = env->regs[15];
|
|
*flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
|
|
| (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
|
|
| (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
|
|
| (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
|
|
| (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
|
|
if (arm_feature(env, ARM_FEATURE_M)) {
|
|
privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
|
|
} else {
|
|
privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
|
|
}
|
|
if (privmode) {
|
|
*flags |= ARM_TBFLAG_PRIV_MASK;
|
|
}
|
|
if (!(access_secure_reg(env))) {
|
|
*flags |= ARM_TBFLAG_NS_MASK;
|
|
}
|
|
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
|
|
|| arm_el_is_aa64(env, 1)) {
|
|
*flags |= ARM_TBFLAG_VFPEN_MASK;
|
|
}
|
|
if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) {
|
|
*flags |= ARM_TBFLAG_CPACR_FPEN_MASK;
|
|
}
|
|
/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
|
|
* states defined in the ARM ARM for software singlestep:
|
|
* SS_ACTIVE PSTATE.SS State
|
|
* 0 x Inactive (the TB flag for SS is always 0)
|
|
* 1 0 Active-pending
|
|
* 1 1 Active-not-pending
|
|
*/
|
|
if (arm_singlestep_active(env)) {
|
|
*flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
|
|
if (env->uncached_cpsr & PSTATE_SS) {
|
|
*flags |= ARM_TBFLAG_PSTATE_SS_MASK;
|
|
}
|
|
}
|
|
*flags |= (extract32(env->cp15.c15_cpar, 0, 2)
|
|
<< ARM_TBFLAG_XSCALE_CPAR_SHIFT);
|
|
}
|
|
|
|
*cs_base = 0;
|
|
}
|
|
|
|
#include "exec/exec-all.h"
|
|
|
|
static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
|
|
{
|
|
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
|
|
env->pc = tb->pc;
|
|
} else {
|
|
env->regs[15] = tb->pc;
|
|
}
|
|
}
|
|
|
|
enum {
|
|
QEMU_PSCI_CONDUIT_DISABLED = 0,
|
|
QEMU_PSCI_CONDUIT_SMC = 1,
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QEMU_PSCI_CONDUIT_HVC = 2,
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};
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#endif
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