709098fd37
While some of the critical fields remain the same, there is variation in
the definition of the control register across the SoC generations.
Reserved regions are adjusted, while in other cases the mutability or
behaviour of fields change.
Introduce a callback to sanitize the value on writes to ensure model
behaviour reflects the hardware.
Fixes: 854123bf8d ("wdt: Add Aspeed watchdog device model")
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210709053107.1829304-2-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
/*
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* ASPEED Watchdog Controller
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*
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* Copyright (C) 2016-2017 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef WDT_ASPEED_H
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#define WDT_ASPEED_H
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#include "hw/misc/aspeed_scu.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_ASPEED_WDT "aspeed.wdt"
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OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
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#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
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#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
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#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
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#define ASPEED_WDT_REGS_MAX (0x20 / 4)
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struct AspeedWDTState {
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/*< private >*/
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SysBusDevice parent_obj;
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QEMUTimer *timer;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t regs[ASPEED_WDT_REGS_MAX];
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AspeedSCUState *scu;
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uint32_t pclk_freq;
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};
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struct AspeedWDTClass {
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SysBusDeviceClass parent_class;
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uint32_t offset;
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uint32_t ext_pulse_width_mask;
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uint32_t reset_ctrl_reg;
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void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
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void (*wdt_reload)(AspeedWDTState *s);
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uint64_t (*sanitize_ctrl)(uint64_t data);
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};
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#endif /* WDT_ASPEED_H */
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