qemu-e2k/target/riscv
Peter Maydell 20d6c7312f RISC-V Changes for 3.2, Part 1
This pull request contains the first set of RISC-V patches I'd like to
 target for the 3.2 development cycle.  It's really just a collection of
 bug fixes with one major new feature: PCIe can now be attached to RISC-V
 guests.
 
 This has passed my usual test of booting the latest Linux RC into a
 Fedora disk image on the virt machine.
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Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1' into staging

RISC-V Changes for 3.2, Part 1

This pull request contains the first set of RISC-V patches I'd like to
target for the 3.2 development cycle.  It's really just a collection of
bug fixes with one major new feature: PCIe can now be attached to RISC-V
guests.

This has passed my usual test of booting the latest Linux RC into a
Fedora disk image on the virt machine.

# gpg: Signature made Fri 21 Dec 2018 16:01:29 GMT
# gpg:                using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>"
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-3.2-part1:
  MAINTAINERS: Mark RISC-V as Supported
  riscv/cpu: use device_class_set_parent_realize
  target/riscv/pmp.c: Fix pmp_decode_napot()
  sifive_uart: Implement interrupt pending register
  RISC-V: Enable second UART on sifive_e and sifive_u
  RISC-V: Fix PLIC pending bitfield reads
  RISC-V: Fix CLINT timecmp low 32-bit writes
  RISC-V: Add hartid and \n to interrupt logging
  sifive_u: Set 'clock-frequency' DT property for SiFive UART
  sifive_u: Add clock DT node for GEM ethernet
  riscv: Enable VGA and PCIE_VGA
  hw/riscv/virt: Connect the gpex PCIe
  hw/riscv/virt: Adjust memory layout spacing
  hw/riscv/virt: Increase the number of interrupts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-03 13:26:30 +00:00
..
Makefile.objs RISC-V: Move non-ops from op_helper to cpu_helper 2018-10-17 13:02:14 -07:00
cpu.c riscv/cpu: use device_class_set_parent_realize 2018-12-20 13:15:10 -08:00
cpu.h RISC-V: Allow setting and clearing multiple irqs 2018-10-17 13:02:09 -07:00
cpu_bits.h RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
cpu_helper.c RISC-V: Add hartid and \n to interrupt logging 2018-12-20 12:08:42 -08:00
cpu_user.h RISC-V Linux User Emulation 2018-03-07 08:30:28 +13:00
fpu_helper.c Clean up includes 2018-12-20 10:29:08 +01:00
gdbstub.c RISC-V GDB Stub 2018-03-07 08:30:28 +13:00
helper.h
instmap.h RISC-V TCG Code Generation 2018-03-07 08:30:28 +13:00
op_helper.c RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
pmp.c target/riscv/pmp.c: Fix pmp_decode_napot() 2018-12-20 12:26:39 -08:00
pmp.h RISC-V Physical Memory Protection 2018-03-07 08:30:28 +13:00
translate.c RISC-V: Respect fences for user-only emulators 2018-11-13 15:12:15 -08:00