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Peter Maydell 4c8c1cc544 -----BEGIN PGP SIGNATURE----- 
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Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.10-pull-request' into staging

# gpg: Signature made Wed 21 Jun 2017 22:00:24 BST
# gpg:                using RSA key 0xF30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier/tags/m68k-for-2.10-pull-request:
  target-m68k: add FPCR and FPSR
  target-m68k: define 96bit FP registers for gdb on 680x0
  target-m68k: use floatx80 internally
  target-m68k: initialize FPU registers
  target-m68k: move fmove CR to a function

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 		2017-06-22 19:01:58 +01:00
..
alpha target/alpha: Use tcg_gen_lookup_and_goto_ptr 2017-06-19 11:11:25 -07:00
arm target/arm: Exit after clearing aarch64 interrupt mask 2017-06-19 11:11:26 -07:00
cris qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
hppa target/hppa: Use tcg_gen_lookup_and_goto_ptr 2017-06-05 09:25:42 -07:00
i386 QAPI patches for 2017-06-09 2017-06-22 11:34:39 +01:00
lm32 qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
m68k target-m68k: add FPCR and FPSR 2017-06-21 22:11:55 +02:00
microblaze cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
mips target/mips: optimize indirect branches 2017-06-05 09:25:42 -07:00
moxie qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
nios2 target/nios2: Fix 64-bit ilp32 compilation 2017-06-05 09:25:42 -07:00
openrisc target/openrisc: Support non-busy idle state using PMR SPR 2017-05-04 09:39:14 +09:00
ppc target/ppc: fix memory leak in kvmppc_is_mem_backend_page_size_ok() 2017-06-08 11:05:31 +10:00
s390x target/s390x: Exit after changing PSW mask 2017-06-19 11:11:25 -07:00
sh4 target/sh4: fix RTE instruction delay slot 2017-05-30 21:00:56 +02:00
sparc shutdown: Add source information to SHUTDOWN and RESET 2017-05-23 13:28:17 +02:00
tilegx migration: Remove unneeded includes of migration/vmstate.h 2017-06-01 18:49:22 +02:00
tricore qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
unicore32 cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
xtensa target/xtensa: handle unknown registers in gdbstub 2017-06-06 02:40:48 -07:00