14e1255991
Add inline routines for convenient access to pci devices with correct (little) endianness. Will be used by MSI-X support. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
292 lines
9.6 KiB
C
292 lines
9.6 KiB
C
#ifndef QEMU_PCI_H
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#define QEMU_PCI_H
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#include "qemu-common.h"
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#include "qdev.h"
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/* PCI includes legacy ISA access. */
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#include "isa.h"
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/* PCI bus */
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extern target_phys_addr_t pci_mem_base;
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#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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/* Class, Vendor and Device IDs from Linux's pci_ids.h */
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#include "pci_ids.h"
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/* QEMU-specific Vendor and Device ID definitions */
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/* IBM (0x1014) */
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#define PCI_DEVICE_ID_IBM_440GX 0x027f
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#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
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/* Hitachi (0x1054) */
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#define PCI_VENDOR_ID_HITACHI 0x1054
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#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
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/* Apple (0x106b) */
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#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
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#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
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#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
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#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
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#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
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/* Realtek (0x10ec) */
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#define PCI_DEVICE_ID_REALTEK_8029 0x8029
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/* Xilinx (0x10ee) */
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#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
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/* Marvell (0x11ab) */
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#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
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/* QEMU/Bochs VGA (0x1234) */
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#define PCI_VENDOR_ID_QEMU 0x1234
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#define PCI_DEVICE_ID_QEMU_VGA 0x1111
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/* VMWare (0x15ad) */
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#define PCI_VENDOR_ID_VMWARE 0x15ad
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#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
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#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
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#define PCI_DEVICE_ID_VMWARE_NET 0x0720
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#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
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#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
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/* Intel (0x8086) */
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#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
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/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
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#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
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#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
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#define PCI_SUBDEVICE_ID_QEMU 0x1100
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#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
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#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
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#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
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#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
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typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
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uint32_t address, uint32_t data, int len);
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typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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uint32_t address, int len);
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typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type);
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typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
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#define PCI_ADDRESS_SPACE_MEM 0x00
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#define PCI_ADDRESS_SPACE_IO 0x01
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#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
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typedef struct PCIIORegion {
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uint32_t addr; /* current PCI mapping address. -1 means not mapped */
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uint32_t size;
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uint8_t type;
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PCIMapIORegionFunc *map_func;
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} PCIIORegion;
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#define PCI_ROM_SLOT 6
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#define PCI_NUM_REGIONS 7
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/* Declarations from linux/pci_regs.h */
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_COMMAND_MASTER 0x4 /* Enable bus master */
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#define PCI_STATUS 0x06 /* 16 bits */
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#define PCI_REVISION_ID 0x08 /* 8 bits */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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#define PCI_HEADER_TYPE 0x0e /* 8 bits */
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#define PCI_HEADER_TYPE_NORMAL 0
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#define PCI_HEADER_TYPE_BRIDGE 1
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#define PCI_HEADER_TYPE_CARDBUS 2
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#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
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#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
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#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */
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#define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */
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#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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#define PCI_MAX_LAT 0x3f /* 8 bits */
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#define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */
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#define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
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#define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */
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/* Bits in the PCI Status Register (PCI 2.3 spec) */
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#define PCI_STATUS_RESERVED1 0x007
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#define PCI_STATUS_INT_STATUS 0x008
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#define PCI_STATUS_CAPABILITIES 0x010
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#define PCI_STATUS_66MHZ 0x020
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#define PCI_STATUS_RESERVED2 0x040
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#define PCI_STATUS_FAST_BACK 0x080
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#define PCI_STATUS_DEVSEL 0x600
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#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
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PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
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PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
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#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
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/* Bits in the PCI Command Register (PCI 2.3 spec) */
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#define PCI_COMMAND_RESERVED 0xf800
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#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
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/* Size of the standard PCI config header */
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#define PCI_CONFIG_HEADER_SIZE 0x40
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/* Size of the standard PCI config space */
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#define PCI_CONFIG_SPACE_SIZE 0x100
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struct PCIDevice {
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DeviceState qdev;
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/* PCI config space */
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uint8_t config[PCI_CONFIG_SPACE_SIZE];
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/* Used to implement R/W bytes */
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uint8_t wmask[PCI_CONFIG_SPACE_SIZE];
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/* the following fields are read only */
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PCIBus *bus;
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int devfn;
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char name[64];
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PCIIORegion io_regions[PCI_NUM_REGIONS];
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/* do not access the following fields */
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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PCIUnregisterFunc *unregister;
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/* IRQ objects for the INTA-INTD pins. */
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qemu_irq *irq;
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/* Current IRQ levels. Used internally by the generic PCI code. */
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int irq_state[4];
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};
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PCIDevice *pci_register_device(PCIBus *bus, const char *name,
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int instance_size, int devfn,
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PCIConfigReadFunc *config_read,
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PCIConfigWriteFunc *config_write);
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int pci_unregister_device(PCIDevice *pci_dev);
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void pci_register_bar(PCIDevice *pci_dev, int region_num,
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func);
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uint32_t pci_default_read_config(PCIDevice *d,
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uint32_t address, int len);
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len);
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void pci_device_save(PCIDevice *s, QEMUFile *f);
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int pci_device_load(PCIDevice *s, QEMUFile *f);
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typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
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typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
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PCIBus *pci_register_bus(DeviceState *parent, const char *name,
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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qemu_irq *pic, int devfn_min, int nirq);
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PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
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const char *default_devaddr);
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void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
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uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
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int pci_bus_num(PCIBus *s);
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void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
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PCIBus *pci_find_bus(int bus_num);
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PCIDevice *pci_find_device(int bus_num, int slot, int function);
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int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp);
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void pci_info(Monitor *mon);
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PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
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pci_map_irq_fn map_irq, const char *name);
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static inline void
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pci_set_word(uint8_t *config, uint16_t val)
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{
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cpu_to_le16wu((uint16_t *)config, val);
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}
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static inline uint16_t
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pci_get_word(uint8_t *config)
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{
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return le16_to_cpupu((uint16_t *)config);
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}
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static inline void
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pci_set_long(uint8_t *config, uint32_t val)
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{
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cpu_to_le32wu((uint32_t *)config, val);
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}
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static inline uint32_t
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pci_get_long(uint8_t *config)
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{
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return le32_to_cpupu((uint32_t *)config);
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}
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static inline void
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pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
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{
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pci_set_word(&pci_config[PCI_VENDOR_ID], val);
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}
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static inline void
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pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
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{
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pci_set_word(&pci_config[PCI_DEVICE_ID], val);
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}
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static inline void
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pci_config_set_class(uint8_t *pci_config, uint16_t val)
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{
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pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
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}
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typedef void (*pci_qdev_initfn)(PCIDevice *dev);
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void pci_qdev_register(const char *name, int size, pci_qdev_initfn init);
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PCIDevice *pci_create(const char *name, const char *devaddr);
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PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
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/* lsi53c895a.c */
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#define LSI_MAX_DEVS 7
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void lsi_scsi_attach(DeviceState *host, BlockDriverState *bd, int id);
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/* vmware_vga.c */
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void pci_vmsvga_init(PCIBus *bus);
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/* usb-uhci.c */
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void usb_uhci_piix3_init(PCIBus *bus, int devfn);
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void usb_uhci_piix4_init(PCIBus *bus, int devfn);
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/* usb-ohci.c */
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void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
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/* prep_pci.c */
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PCIBus *pci_prep_init(qemu_irq *pic);
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/* apb_pci.c */
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PCIBus *pci_apb_init(target_phys_addr_t special_base,
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target_phys_addr_t mem_base,
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qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
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/* sh_pci.c */
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PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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qemu_irq *pic, int devfn_min, int nirq);
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#endif
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