f8cfdd2038
this name is used by capstone and will lead to a build failure of QEMU, when capstone is enabled. So we rename it to tricore_has_feature(), to match has_feature() in translate.c. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1774 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20230721060605.76636-1-kbastian@mail.uni-paderborn.de>
409 lines
9.2 KiB
C
409 lines
9.2 KiB
C
/*
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* TriCore emulation for qemu: main CPU struct.
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*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TRICORE_CPU_H
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#define TRICORE_CPU_H
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#include "cpu-qom.h"
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#include "hw/registerfields.h"
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#include "exec/cpu-defs.h"
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#include "qemu/cpu-float.h"
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#include "tricore-defs.h"
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typedef struct CPUArchState {
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/* GPR Register */
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uint32_t gpr_a[16];
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uint32_t gpr_d[16];
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/* CSFR Register */
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uint32_t PCXI;
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/* Frequently accessed PSW_USB bits are stored separately for efficiency.
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This contains all the other bits. Use psw_{read,write} to access
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the whole PSW. */
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uint32_t PSW;
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/* PSW flag cache for faster execution
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*/
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uint32_t PSW_USB_C;
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uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
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uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
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uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
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uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
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uint32_t PC;
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uint32_t SYSCON;
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uint32_t CPU_ID;
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uint32_t CORE_ID;
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uint32_t BIV;
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uint32_t BTV;
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uint32_t ISP;
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uint32_t ICR;
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uint32_t FCX;
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uint32_t LCX;
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uint32_t COMPAT;
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/* Mem Protection Register */
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uint32_t DPR0_0L;
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uint32_t DPR0_0U;
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uint32_t DPR0_1L;
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uint32_t DPR0_1U;
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uint32_t DPR0_2L;
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uint32_t DPR0_2U;
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uint32_t DPR0_3L;
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uint32_t DPR0_3U;
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uint32_t DPR1_0L;
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uint32_t DPR1_0U;
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uint32_t DPR1_1L;
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uint32_t DPR1_1U;
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uint32_t DPR1_2L;
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uint32_t DPR1_2U;
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uint32_t DPR1_3L;
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uint32_t DPR1_3U;
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uint32_t DPR2_0L;
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uint32_t DPR2_0U;
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uint32_t DPR2_1L;
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uint32_t DPR2_1U;
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uint32_t DPR2_2L;
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uint32_t DPR2_2U;
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uint32_t DPR2_3L;
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uint32_t DPR2_3U;
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uint32_t DPR3_0L;
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uint32_t DPR3_0U;
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uint32_t DPR3_1L;
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uint32_t DPR3_1U;
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uint32_t DPR3_2L;
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uint32_t DPR3_2U;
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uint32_t DPR3_3L;
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uint32_t DPR3_3U;
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uint32_t CPR0_0L;
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uint32_t CPR0_0U;
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uint32_t CPR0_1L;
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uint32_t CPR0_1U;
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uint32_t CPR0_2L;
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uint32_t CPR0_2U;
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uint32_t CPR0_3L;
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uint32_t CPR0_3U;
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uint32_t CPR1_0L;
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uint32_t CPR1_0U;
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uint32_t CPR1_1L;
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uint32_t CPR1_1U;
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uint32_t CPR1_2L;
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uint32_t CPR1_2U;
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uint32_t CPR1_3L;
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uint32_t CPR1_3U;
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uint32_t CPR2_0L;
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uint32_t CPR2_0U;
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uint32_t CPR2_1L;
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uint32_t CPR2_1U;
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uint32_t CPR2_2L;
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uint32_t CPR2_2U;
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uint32_t CPR2_3L;
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uint32_t CPR2_3U;
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uint32_t CPR3_0L;
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uint32_t CPR3_0U;
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uint32_t CPR3_1L;
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uint32_t CPR3_1U;
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uint32_t CPR3_2L;
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uint32_t CPR3_2U;
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uint32_t CPR3_3L;
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uint32_t CPR3_3U;
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uint32_t DPM0;
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uint32_t DPM1;
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uint32_t DPM2;
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uint32_t DPM3;
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uint32_t CPM0;
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uint32_t CPM1;
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uint32_t CPM2;
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uint32_t CPM3;
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/* Memory Management Registers */
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uint32_t MMU_CON;
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uint32_t MMU_ASI;
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uint32_t MMU_TVA;
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uint32_t MMU_TPA;
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uint32_t MMU_TPX;
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uint32_t MMU_TFA;
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/* {1.3.1 only */
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uint32_t BMACON;
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uint32_t SMACON;
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uint32_t DIEAR;
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uint32_t DIETR;
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uint32_t CCDIER;
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uint32_t MIECON;
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uint32_t PIEAR;
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uint32_t PIETR;
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uint32_t CCPIER;
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/*} */
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/* Debug Registers */
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uint32_t DBGSR;
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uint32_t EXEVT;
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uint32_t CREVT;
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uint32_t SWEVT;
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uint32_t TR0EVT;
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uint32_t TR1EVT;
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uint32_t DMS;
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uint32_t DCX;
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uint32_t DBGTCR;
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uint32_t CCTRL;
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uint32_t CCNT;
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uint32_t ICNT;
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uint32_t M1CNT;
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uint32_t M2CNT;
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uint32_t M3CNT;
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/* Floating Point Registers */
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float_status fp_status;
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/* Internal CPU feature flags. */
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uint64_t features;
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} CPUTriCoreState;
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/**
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* TriCoreCPU:
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* @env: #CPUTriCoreState
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*
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* A TriCore CPU.
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*/
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUTriCoreState env;
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};
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hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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FIELD(PCXI, PCPN_13, 24, 8)
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FIELD(PCXI, PCPN_161, 22, 8)
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FIELD(PCXI, PIE_13, 23, 1)
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FIELD(PCXI, PIE_161, 21, 1)
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FIELD(PCXI, UL_13, 22, 1)
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FIELD(PCXI, UL_161, 20, 1)
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FIELD(PCXI, PCXS, 16, 4)
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FIELD(PCXI, PCXO, 0, 16)
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uint32_t pcxi_get_ul(CPUTriCoreState *env);
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uint32_t pcxi_get_pie(CPUTriCoreState *env);
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uint32_t pcxi_get_pcpn(CPUTriCoreState *env);
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uint32_t pcxi_get_pcxs(CPUTriCoreState *env);
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uint32_t pcxi_get_pcxo(CPUTriCoreState *env);
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void pcxi_set_ul(CPUTriCoreState *env, uint32_t val);
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void pcxi_set_pie(CPUTriCoreState *env, uint32_t val);
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void pcxi_set_pcpn(CPUTriCoreState *env, uint32_t val);
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FIELD(ICR, IE_161, 15, 1)
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FIELD(ICR, IE_13, 8, 1)
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FIELD(ICR, PIPN, 16, 8)
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FIELD(ICR, CCPN, 0, 8)
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uint32_t icr_get_ie(CPUTriCoreState *env);
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uint32_t icr_get_ccpn(CPUTriCoreState *env);
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void icr_set_ccpn(CPUTriCoreState *env, uint32_t val);
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void icr_set_ie(CPUTriCoreState *env, uint32_t val);
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#define MASK_PSW_USB 0xff000000
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#define MASK_USB_C 0x80000000
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#define MASK_USB_V 0x40000000
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#define MASK_USB_SV 0x20000000
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#define MASK_USB_AV 0x10000000
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#define MASK_USB_SAV 0x08000000
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#define MASK_PSW_PRS 0x00003000
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#define MASK_PSW_IO 0x00000c00
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#define MASK_PSW_IS 0x00000200
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#define MASK_PSW_GW 0x00000100
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#define MASK_PSW_CDE 0x00000080
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#define MASK_PSW_CDC 0x0000007f
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#define MASK_PSW_FPU_RM 0x3000000
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#define MASK_SYSCON_PRO_TEN 0x2
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#define MASK_SYSCON_FCD_SF 0x1
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#define MASK_CPUID_MOD 0xffff0000
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#define MASK_CPUID_MOD_32B 0x0000ff00
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#define MASK_CPUID_REV 0x000000ff
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#define MASK_FCX_FCXS 0x000f0000
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#define MASK_FCX_FCXO 0x0000ffff
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#define MASK_LCX_LCXS 0x000f0000
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#define MASK_LCX_LCX0 0x0000ffff
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#define MASK_DBGSR_DE 0x1
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#define MASK_DBGSR_HALT 0x6
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#define MASK_DBGSR_SUSP 0x10
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#define MASK_DBGSR_PREVSUSP 0x20
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#define MASK_DBGSR_PEVT 0x40
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#define MASK_DBGSR_EVTSRC 0x1f00
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enum tricore_priv_levels {
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TRICORE_PRIV_UM0 = 0x0, /* user mode-0 flag */
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TRICORE_PRIV_UM1 = 0x1, /* user mode-1 flag */
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TRICORE_PRIV_SM = 0x2, /* kernel mode flag */
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};
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enum tricore_features {
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TRICORE_FEATURE_13,
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TRICORE_FEATURE_131,
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TRICORE_FEATURE_16,
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TRICORE_FEATURE_161,
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TRICORE_FEATURE_162,
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};
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static inline int tricore_has_feature(CPUTriCoreState *env, int feature)
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{
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return (env->features & (1ULL << feature)) != 0;
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}
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/* TriCore Traps Classes*/
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enum {
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TRAPC_NONE = -1,
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TRAPC_MMU = 0,
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TRAPC_PROT = 1,
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TRAPC_INSN_ERR = 2,
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TRAPC_CTX_MNG = 3,
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TRAPC_SYSBUS = 4,
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TRAPC_ASSERT = 5,
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TRAPC_SYSCALL = 6,
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TRAPC_NMI = 7,
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TRAPC_IRQ = 8
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};
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/* Class 0 TIN */
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enum {
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TIN0_VAF = 0,
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TIN0_VAP = 1,
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};
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/* Class 1 TIN */
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enum {
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TIN1_PRIV = 1,
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TIN1_MPR = 2,
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TIN1_MPW = 3,
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TIN1_MPX = 4,
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TIN1_MPP = 5,
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TIN1_MPN = 6,
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TIN1_GRWP = 7,
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};
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/* Class 2 TIN */
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enum {
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TIN2_IOPC = 1,
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TIN2_UOPC = 2,
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TIN2_OPD = 3,
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TIN2_ALN = 4,
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TIN2_MEM = 5,
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};
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/* Class 3 TIN */
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enum {
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TIN3_FCD = 1,
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TIN3_CDO = 2,
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TIN3_CDU = 3,
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TIN3_FCU = 4,
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TIN3_CSU = 5,
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TIN3_CTYP = 6,
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TIN3_NEST = 7,
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};
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/* Class 4 TIN */
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enum {
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TIN4_PSE = 1,
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TIN4_DSE = 2,
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TIN4_DAE = 3,
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TIN4_CAE = 4,
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TIN4_PIE = 5,
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TIN4_DIE = 6,
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};
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/* Class 5 TIN */
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enum {
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TIN5_OVF = 1,
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TIN5_SOVF = 1,
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};
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/* Class 6 TIN
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*
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* Is always TIN6_SYS
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*/
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/* Class 7 TIN */
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enum {
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TIN7_NMI = 0,
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};
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uint32_t psw_read(CPUTriCoreState *env);
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void psw_write(CPUTriCoreState *env, uint32_t val);
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int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
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int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
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void fpu_set_state(CPUTriCoreState *env);
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#define MMU_USER_IDX 2
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void tricore_cpu_list(void);
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#define cpu_list tricore_cpu_list
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static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
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{
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return 0;
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}
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#include "exec/cpu-all.h"
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FIELD(TB_FLAGS, PRIV, 0, 2)
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void cpu_state_reset(CPUTriCoreState *s);
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void tricore_tcg_init(void);
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static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
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uint64_t *cs_base, uint32_t *flags)
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{
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uint32_t new_flags = 0;
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*pc = env->PC;
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*cs_base = 0;
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new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV,
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extract32(env->PSW, 10, 2));
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*flags = new_flags;
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}
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#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
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#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
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#define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
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/* helpers.c */
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bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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#endif /* TRICORE_CPU_H */
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