581 lines
14 KiB
C
581 lines
14 KiB
C
/*
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* Inter-Thread Communication Unit emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "hw/misc/mips_itu.h"
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#define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
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/* Initialize as 4kB area to fit all 32 cells with default 128B grain.
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Storage may be resized by the software. */
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#define ITC_STORAGE_ADDRSPACE_SZ 0x1000
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#define ITC_FIFO_NUM_MAX 16
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#define ITC_SEMAPH_NUM_MAX 16
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#define ITC_AM1_NUMENTRIES_OFS 20
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#define ITC_CELL_PV_MAX_VAL 0xFFFF
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#define ITC_CELL_TAG_FIFO_DEPTH 28
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#define ITC_CELL_TAG_FIFO_PTR 18
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#define ITC_CELL_TAG_FIFO 17
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#define ITC_CELL_TAG_T 16
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#define ITC_CELL_TAG_F 1
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#define ITC_CELL_TAG_E 0
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#define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
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#define ITC_AM0_EN_MASK 0x1
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#define ITC_AM1_ADDR_MASK_MASK 0x1FC00
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#define ITC_AM1_ENTRY_GRAIN_MASK 0x7
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typedef enum ITCView {
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ITCVIEW_BYPASS = 0,
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ITCVIEW_CONTROL = 1,
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ITCVIEW_EF_SYNC = 2,
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ITCVIEW_EF_TRY = 3,
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ITCVIEW_PV_SYNC = 4,
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ITCVIEW_PV_TRY = 5,
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ITCVIEW_PV_ICR0 = 15,
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} ITCView;
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#define ITC_ICR0_CELL_NUM 16
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#define ITC_ICR0_BLK_GRAIN 8
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#define ITC_ICR0_BLK_GRAIN_MASK 0x7
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#define ITC_ICR0_ERR_AXI 2
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#define ITC_ICR0_ERR_PARITY 1
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#define ITC_ICR0_ERR_EXEC 0
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MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
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{
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return &itu->tag_io;
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}
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static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
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{
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MIPSITUState *tag = (MIPSITUState *)opaque;
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uint64_t index = addr >> 3;
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if (index >= ITC_ADDRESSMAP_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
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return 0;
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}
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return tag->ITCAddressMap[index];
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}
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void itc_reconfigure(MIPSITUState *tag)
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{
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uint64_t *am = &tag->ITCAddressMap[0];
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MemoryRegion *mr = &tag->storage_io;
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hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
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uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
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bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
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if (tag->saar_present) {
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address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4;
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size = 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
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is_enabled = *(uint64_t *) tag->saar & 1;
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}
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memory_region_transaction_begin();
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if (!(size & (size - 1))) {
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memory_region_set_size(mr, size);
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}
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memory_region_set_address(mr, address);
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memory_region_set_enabled(mr, is_enabled);
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memory_region_transaction_commit();
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}
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static void itc_tag_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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MIPSITUState *tag = (MIPSITUState *)opaque;
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uint64_t *am = &tag->ITCAddressMap[0];
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uint64_t am_old, mask;
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uint64_t index = addr >> 3;
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switch (index) {
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case 0:
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mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
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break;
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case 1:
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mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
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return;
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}
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am_old = am[index];
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am[index] = (data & mask) | (am_old & ~mask);
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if (am_old != am[index]) {
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itc_reconfigure(tag);
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}
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}
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static const MemoryRegionOps itc_tag_ops = {
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.read = itc_tag_read,
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.write = itc_tag_write,
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.impl = {
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.max_access_size = 8,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static inline uint32_t get_num_cells(MIPSITUState *s)
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{
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return s->num_fifo + s->num_semaphores;
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}
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static inline ITCView get_itc_view(hwaddr addr)
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{
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return (addr >> 3) & 0xf;
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}
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static inline int get_cell_stride_shift(const MIPSITUState *s)
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{
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/* Minimum interval (for EntryGain = 0) is 128 B */
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if (s->saar_present) {
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return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &
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ITC_ICR0_BLK_GRAIN_MASK);
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} else {
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return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
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}
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}
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static inline ITCStorageCell *get_cell(MIPSITUState *s,
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hwaddr addr)
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{
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uint32_t cell_idx = addr >> get_cell_stride_shift(s);
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uint32_t num_cells = get_num_cells(s);
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if (cell_idx >= num_cells) {
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cell_idx = num_cells - 1;
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}
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return &s->cell[cell_idx];
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}
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static void wake_blocked_threads(ITCStorageCell *c)
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{
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CPUState *cs;
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CPU_FOREACH(cs) {
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if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
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cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
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}
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}
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c->blocked_threads = 0;
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}
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static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c)
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{
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c->blocked_threads |= 1ULL << current_cpu->cpu_index;
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current_cpu->halted = 1;
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current_cpu->exception_index = EXCP_HLT;
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cpu_loop_exit_restore(current_cpu, current_cpu->mem_io_pc);
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}
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/* ITC Bypass View */
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static inline uint64_t view_bypass_read(ITCStorageCell *c)
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{
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if (c->tag.FIFO) {
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return c->data[c->fifo_out];
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} else {
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return c->data[0];
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}
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}
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static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
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{
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if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
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int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
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c->data[idx] = val;
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}
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/* ignore a write to the semaphore cell */
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}
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/* ITC Control View */
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static inline uint64_t view_control_read(ITCStorageCell *c)
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{
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return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
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(c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
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(c->tag.FIFO << ITC_CELL_TAG_FIFO) |
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(c->tag.T << ITC_CELL_TAG_T) |
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(c->tag.E << ITC_CELL_TAG_E) |
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(c->tag.F << ITC_CELL_TAG_F);
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}
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static inline void view_control_write(ITCStorageCell *c, uint64_t val)
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{
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c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
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c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
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c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
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if (c->tag.E) {
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c->tag.FIFOPtr = 0;
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}
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}
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/* ITC Empty/Full View */
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static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
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{
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uint64_t ret = 0;
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if (!c->tag.FIFO) {
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return 0;
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}
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c->tag.F = 0;
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if (blocking && c->tag.E) {
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block_thread_and_exit(c);
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}
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if (c->blocked_threads) {
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wake_blocked_threads(c);
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}
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if (c->tag.FIFOPtr > 0) {
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ret = c->data[c->fifo_out];
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c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
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c->tag.FIFOPtr--;
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}
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if (c->tag.FIFOPtr == 0) {
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c->tag.E = 1;
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}
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return ret;
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}
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static uint64_t view_ef_sync_read(ITCStorageCell *c)
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{
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return view_ef_common_read(c, true);
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}
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static uint64_t view_ef_try_read(ITCStorageCell *c)
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{
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return view_ef_common_read(c, false);
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}
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static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
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bool blocking)
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{
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if (!c->tag.FIFO) {
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return;
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}
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c->tag.E = 0;
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if (blocking && c->tag.F) {
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block_thread_and_exit(c);
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}
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if (c->blocked_threads) {
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wake_blocked_threads(c);
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}
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if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
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int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
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c->data[idx] = val;
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c->tag.FIFOPtr++;
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}
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if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
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c->tag.F = 1;
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}
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}
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static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
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{
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view_ef_common_write(c, val, true);
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}
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static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
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{
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view_ef_common_write(c, val, false);
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}
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/* ITC P/V View */
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static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking)
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{
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uint64_t ret = c->data[0];
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if (c->tag.FIFO) {
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return 0;
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}
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if (c->data[0] > 0) {
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c->data[0]--;
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} else if (blocking) {
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block_thread_and_exit(c);
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}
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return ret;
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}
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static uint64_t view_pv_sync_read(ITCStorageCell *c)
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{
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return view_pv_common_read(c, true);
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}
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static uint64_t view_pv_try_read(ITCStorageCell *c)
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{
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return view_pv_common_read(c, false);
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}
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static inline void view_pv_common_write(ITCStorageCell *c)
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{
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if (c->tag.FIFO) {
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return;
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}
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if (c->data[0] < ITC_CELL_PV_MAX_VAL) {
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c->data[0]++;
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}
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if (c->blocked_threads) {
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wake_blocked_threads(c);
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}
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}
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static void view_pv_sync_write(ITCStorageCell *c)
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{
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view_pv_common_write(c);
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}
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static void view_pv_try_write(ITCStorageCell *c)
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{
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view_pv_common_write(c);
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}
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static void raise_exception(int excp)
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{
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current_cpu->exception_index = excp;
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cpu_loop_exit(current_cpu);
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}
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static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
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{
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MIPSITUState *s = (MIPSITUState *)opaque;
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ITCStorageCell *cell = get_cell(s, addr);
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ITCView view = get_itc_view(addr);
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uint64_t ret = -1;
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switch (size) {
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case 1:
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case 2:
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s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
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raise_exception(EXCP_DBE);
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return 0;
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}
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switch (view) {
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case ITCVIEW_BYPASS:
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ret = view_bypass_read(cell);
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break;
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case ITCVIEW_CONTROL:
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ret = view_control_read(cell);
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break;
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case ITCVIEW_EF_SYNC:
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ret = view_ef_sync_read(cell);
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break;
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case ITCVIEW_EF_TRY:
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ret = view_ef_try_read(cell);
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break;
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case ITCVIEW_PV_SYNC:
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ret = view_pv_sync_read(cell);
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break;
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case ITCVIEW_PV_TRY:
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ret = view_pv_try_read(cell);
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break;
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case ITCVIEW_PV_ICR0:
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ret = s->icr0;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"itc_storage_read: Bad ITC View %d\n", (int)view);
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break;
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}
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return ret;
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}
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static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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MIPSITUState *s = (MIPSITUState *)opaque;
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ITCStorageCell *cell = get_cell(s, addr);
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ITCView view = get_itc_view(addr);
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switch (size) {
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case 1:
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case 2:
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s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
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raise_exception(EXCP_DBE);
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return;
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}
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switch (view) {
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case ITCVIEW_BYPASS:
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view_bypass_write(cell, data);
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break;
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case ITCVIEW_CONTROL:
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view_control_write(cell, data);
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break;
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case ITCVIEW_EF_SYNC:
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view_ef_sync_write(cell, data);
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break;
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case ITCVIEW_EF_TRY:
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view_ef_try_write(cell, data);
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break;
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case ITCVIEW_PV_SYNC:
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view_pv_sync_write(cell);
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break;
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case ITCVIEW_PV_TRY:
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view_pv_try_write(cell);
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break;
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case ITCVIEW_PV_ICR0:
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if (data & 0x7) {
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/* clear ERROR bits */
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s->icr0 &= ~(data & 0x7);
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}
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/* set BLK_GRAIN */
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s->icr0 &= ~0x700;
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s->icr0 |= data & 0x700;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"itc_storage_write: Bad ITC View %d\n", (int)view);
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break;
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}
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}
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static const MemoryRegionOps itc_storage_ops = {
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.read = itc_storage_read,
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.write = itc_storage_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void itc_reset_cells(MIPSITUState *s)
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{
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int i;
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memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
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for (i = 0; i < s->num_fifo; i++) {
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s->cell[i].tag.E = 1;
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s->cell[i].tag.FIFO = 1;
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s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
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}
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}
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static void mips_itu_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MIPSITUState *s = MIPS_ITU(obj);
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memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
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"mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
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sysbus_init_mmio(sbd, &s->storage_io);
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memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
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"mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
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}
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|
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static void mips_itu_realize(DeviceState *dev, Error **errp)
|
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{
|
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MIPSITUState *s = MIPS_ITU(dev);
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|
|
if (s->num_fifo > ITC_FIFO_NUM_MAX) {
|
|
error_setg(errp, "Exceed maximum number of FIFO cells: %d",
|
|
s->num_fifo);
|
|
return;
|
|
}
|
|
if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
|
|
error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
|
|
s->num_semaphores);
|
|
return;
|
|
}
|
|
|
|
s->cell = g_new(ITCStorageCell, get_num_cells(s));
|
|
}
|
|
|
|
static void mips_itu_reset(DeviceState *dev)
|
|
{
|
|
MIPSITUState *s = MIPS_ITU(dev);
|
|
|
|
if (s->saar_present) {
|
|
*(uint64_t *) s->saar = 0x11 << 1;
|
|
s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;
|
|
} else {
|
|
s->ITCAddressMap[0] = 0;
|
|
s->ITCAddressMap[1] =
|
|
((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
|
|
(get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
|
|
}
|
|
itc_reconfigure(s);
|
|
|
|
itc_reset_cells(s);
|
|
}
|
|
|
|
static Property mips_itu_properties[] = {
|
|
DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo,
|
|
ITC_FIFO_NUM_MAX),
|
|
DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,
|
|
ITC_SEMAPH_NUM_MAX),
|
|
DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void mips_itu_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->props = mips_itu_properties;
|
|
dc->realize = mips_itu_realize;
|
|
dc->reset = mips_itu_reset;
|
|
}
|
|
|
|
static const TypeInfo mips_itu_info = {
|
|
.name = TYPE_MIPS_ITU,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(MIPSITUState),
|
|
.instance_init = mips_itu_init,
|
|
.class_init = mips_itu_class_init,
|
|
};
|
|
|
|
static void mips_itu_register_types(void)
|
|
{
|
|
type_register_static(&mips_itu_info);
|
|
}
|
|
|
|
type_init(mips_itu_register_types)
|