Jonathan Cameron 18cef1c6a5 pci-bridge/cxl_downstream: Add a CXL switch downstream port ... Emulation of a simple CXL Switch downstream port. The Device ID has been allocated for this use. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20220616145126.8002-3-Jonathan.Cameron@huawei.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2022-06-16 12:54:57 -04:00
..
cxl_downstream.c	pci-bridge/cxl_downstream: Add a CXL switch downstream port	2022-06-16 12:54:57 -04:00
cxl_root_port.c	hw/cxl/rp: Add a root port	2022-05-13 06:13:36 -04:00
cxl_upstream.c	pci-bridge/cxl_upstream: Add a CXL switch upstream port	2022-06-16 12:54:57 -04:00
dec.c
dec.h
gen_pcie_root_port.c
i82801b11.c
ioh3420.c
Kconfig	hw/cxl/rp: Add a root port	2022-05-13 06:13:36 -04:00
meson.build	pci-bridge/cxl_downstream: Add a CXL switch downstream port	2022-06-16 12:54:57 -04:00
pci_bridge_dev.c
pci_expander_bridge_stubs.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
pci_expander_bridge.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
pcie_pci_bridge.c
pcie_root_port.c	hw/cxl/rp: Add a root port	2022-05-13 06:13:36 -04:00
simba.c
xio3130_downstream.c	pci: expose TYPE_XIO3130_DOWNSTREAM name	2022-03-06 05:08:23 -05:00
xio3130_upstream.c	pci-bridge/xio3130_upstream: Fix error handling	2022-03-06 05:08:23 -05:00