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qemu-e2k/target/mips
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Alex Richardson dda97e385b target/mips: Fix ADD.S FPU instruction 
After merging latest QEMU upstream into our CHERI fork,
I noticed that some of the FPU tests in our MIPS baremetal
testsuite [*] started failing.
It turns out commit 1ace099f2a accidentally changed add.s
into a subtract.

[*] https://github.com/CTSRD-CHERI/cheritest

Fixes: 1ace099f2a ("target/mips: fpu: Demacro ADD.<D|S|PS>")
Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200703161515.25966-1-Alexander.Richardson@cl.cam.ac.uk>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-07-14 21:49:33 +02:00
..
cp0_helper.c target/mips: Remove identical if/else branches 2020-07-14 21:49:33 +02:00
cp0_timer.c target/mips: Style improvements in cp0_timer.c 2019-08-19 19:53:37 +02:00
cpu-param.h target/mips: Support variable page size 2020-06-01 13:28:21 +02:00
cpu-qom.h cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
cpu.c cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
cpu.h target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
dsp_helper.c target/mips: Clean up dsp_helper.c 2019-06-01 20:20:20 +02:00
fpu_helper.c target/mips: Fix ADD.S FPU instruction 2020-07-14 21:49:33 +02:00
gdbstub.c gdbstub: extend GByteArray to read register helpers 2020-03-17 17:38:38 +00:00
helper.c target/mips: Add implementation of GINVT instruction 2020-01-29 19:28:52 +01:00
helper.h target/mips: msa: Split helpers for MULV.<B|H|W|D> 2020-06-15 20:51:04 +02:00
internal.h target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
kvm_mips.h hw/mips: Implement the kvm_type() hook in MachineClass 2020-06-27 19:35:39 +02:00
kvm.c hw/mips: Implement the kvm_type() hook in MachineClass 2020-06-27 19:35:39 +02:00
lmmi_helper.c target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
machine.c target/mips: Add more CP0 register for save/restore 2020-06-01 13:28:21 +02:00
Makefile.objs target/mips: Add Loongson-3 CPU definition 2020-06-09 17:32:45 +02:00
mips-defs.h target/mips: Add comments for vendor-specific ASEs 2020-06-15 20:33:16 +02:00
mips-semi.c target/mips: semihosting: Remove 'uhi_done' label in helper_do_semihosting() 2020-01-29 19:28:52 +01:00
msa_helper.c target/mips: msa: Split helpers for MULV.<B|H|W|D> 2020-06-15 20:51:04 +02:00
op_helper.c target/mips: Separate FPU-related helpers into their own file 2020-02-04 08:53:54 +01:00
TODO Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
trace-events trace-events: Shorten file names in comments 2019-03-22 16:18:07 +00:00
translate_init.inc.c target/mips: Enable hardware page table walker and CMGCR features for P5600 2020-06-09 17:32:45 +02:00
translate.c target/mips: msa: Split helpers for MULV.<B|H|W|D> 2020-06-15 20:51:04 +02:00