qemu-e2k/target/riscv
Peter Maydell 4fa485a78e target/riscv: Convert to 3-phase reset
Convert the riscv CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-id: 20221124115023.2437291-15-peter.maydell@linaro.org
2022-12-16 15:58:15 +00:00
..
insn_trans
arch_dump.c dump: Replace opaque DumpState pointer with a typed one 2022-10-06 19:30:43 +04:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h
cpu_helper.c
cpu_user.h
cpu-param.h
cpu.c target/riscv: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
cpu.h target/riscv: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
crypto_helper.c
csr.c
debug.c cleanup: Tweak and re-run return_directly.cocci 2022-12-14 16:19:35 +01:00
debug.h
fpu_helper.c
gdbstub.c
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c kvm: allow target-specific accelerator properties 2022-10-10 09:23:16 +02:00
m128_helper.c
machine.c
meson.build
monitor.c
op_helper.c
pmp.c target/riscv: pmp: Fixup TLB size calculation 2022-10-14 14:36:19 +10:00
pmp.h
pmu.c
pmu.h
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c
vector_helper.c cleanup: Tweak and re-run return_directly.cocci 2022-12-14 16:19:35 +01:00
XVentanaCondOps.decode