192 lines
6.2 KiB
C
192 lines
6.2 KiB
C
/*
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* QEMU IDE Emulation: PCI VIA82C686B support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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* Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h>
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#include <hw/pc.h>
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#include <hw/pci.h>
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#include <hw/isa.h>
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#include "block.h"
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#include "block_int.h"
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#include "sysemu.h"
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#include "dma.h"
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#include <hw/ide/pci.h>
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static uint32_t bmdma_readb(void *opaque, uint32_t addr)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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switch (addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 2:
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val = bm->status;
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break;
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default:
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val = 0xff;
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break;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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BMDMAState *bm = opaque;
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#ifdef DEBUG_IDE
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printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
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#endif
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switch (addr & 3) {
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case 2:
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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break;
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default:;
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}
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}
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static void bmdma_map(PCIDevice *pci_dev, int region_num,
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pcibus_t addr, pcibus_t size, int type)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
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int i;
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for(i = 0;i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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d->bus[i].bmdma = bm;
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bm->bus = d->bus+i;
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qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
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register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
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register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
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register_ioport_read(addr, 4, 1, bmdma_readb, bm);
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register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
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register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
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register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
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register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
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register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
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register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
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addr += 8;
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}
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}
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static void via_reset(void *opaque)
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{
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PCIIDEState *d = opaque;
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uint8_t *pci_conf = d->dev.config;
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int i;
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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ide_dma_reset(&d->bmdma[i]);
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}
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
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PCI_STATUS_DEVSEL_MEDIUM);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
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pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
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/* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
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pci_set_long(pci_conf + 0x40, 0x0a090600);
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/* IDE misc configuration 1/2/3 */
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pci_set_long(pci_conf + 0x44, 0x00c00068);
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/* IDE Timing control */
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pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
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/* IDE Address Setup Time */
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pci_set_long(pci_conf + 0x4c, 0x000000ff);
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/* UltraDMA Extended Timing Control*/
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pci_set_long(pci_conf + 0x50, 0x07070707);
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/* UltraDMA FIFO Control */
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pci_set_long(pci_conf + 0x54, 0x00000004);
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/* IDE primary sector size */
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pci_set_long(pci_conf + 0x60, 0x00000200);
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/* IDE secondary sector size */
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pci_set_long(pci_conf + 0x68, 0x00000200);
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/* PCI PM Block */
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pci_set_long(pci_conf + 0xc0, 0x00020001);
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}
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/* via ide func */
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static int vt82c686b_ide_initfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);;
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uint8_t *pci_conf = d->dev.config;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_IDE);
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pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
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pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
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pci_config_set_revision(pci_conf,0x06); /* Revision 0.6 */
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pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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qemu_register_reset(via_reset, d);
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pci_register_bar((PCIDevice *)d, 4, 0x10,
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PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
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vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
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ide_bus_new(&d->bus[0], &d->dev.qdev);
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ide_bus_new(&d->bus[1], &d->dev.qdev);
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ide_init2(&d->bus[0], isa_reserve_irq(14));
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ide_init2(&d->bus[1], isa_reserve_irq(15));
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ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
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ide_init_ioport(&d->bus[1], 0x170, 0x376);
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return 0;
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}
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void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create_simple(bus, devfn, "via-ide");
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pci_ide_create_devs(dev, hd_table);
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}
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static PCIDeviceInfo via_ide_info = {
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.qdev.name = "via-ide",
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.qdev.size = sizeof(PCIIDEState),
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.qdev.no_user = 1,
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.init = vt82c686b_ide_initfn,
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};
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static void via_ide_register(void)
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{
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pci_qdev_register(&via_ide_info);
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}
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device_init(via_ide_register);
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