324 lines
9.4 KiB
C
324 lines
9.4 KiB
C
/*
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* Kvaser PCI CAN device (SJA1000 based) emulation
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*
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* Copyright (c) 2013-2014 Jin Yang
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* Copyright (c) 2014-2018 Pavel Pisa
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*
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* Partially based on educational PCIexpress APOHW hardware
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* emulator used fro class A0B36APO at CTU FEE course by
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* Rostislav Lisovy and Pavel Pisa
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*
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* Initial development supported by Google GSoC 2013 from RTEMS project slot
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/event_notifier.h"
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#include "qemu/module.h"
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#include "qemu/thread.h"
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#include "qemu/sockets.h"
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#include "qapi/error.h"
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#include "chardev/char.h"
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#include "hw/irq.h"
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#include "hw/pci/pci.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "net/can_emu.h"
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#include "can_sja1000.h"
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#include "qom/object.h"
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#define TYPE_CAN_PCI_DEV "kvaser_pci"
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typedef struct KvaserPCIState KvaserPCIState;
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DECLARE_INSTANCE_CHECKER(KvaserPCIState, KVASER_PCI_DEV,
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TYPE_CAN_PCI_DEV)
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#ifndef KVASER_PCI_VENDOR_ID1
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#define KVASER_PCI_VENDOR_ID1 0x10e8 /* the PCI device and vendor IDs */
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#endif
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#ifndef KVASER_PCI_DEVICE_ID1
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#define KVASER_PCI_DEVICE_ID1 0x8406
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#endif
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#define KVASER_PCI_S5920_RANGE 0x80
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#define KVASER_PCI_SJA_RANGE 0x80
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#define KVASER_PCI_XILINX_RANGE 0x8
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#define KVASER_PCI_BYTES_PER_SJA 0x20
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#define S5920_OMB 0x0C
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#define S5920_IMB 0x1C
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#define S5920_MBEF 0x34
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#define S5920_INTCSR 0x38
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#define S5920_RCR 0x3C
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#define S5920_PTCR 0x60
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#define S5920_INTCSR_ADDON_INTENABLE_M 0x2000
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#define S5920_INTCSR_INTERRUPT_ASSERTED_M 0x800000
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#define KVASER_PCI_XILINX_VERINT 7 /* Lower nibble simulate interrupts,
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high nibble version number. */
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#define KVASER_PCI_XILINX_VERSION_NUMBER 13
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struct KvaserPCIState {
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/*< private >*/
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PCIDevice dev;
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/*< public >*/
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MemoryRegion s5920_io;
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MemoryRegion sja_io;
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MemoryRegion xilinx_io;
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CanSJA1000State sja_state;
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qemu_irq irq;
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uint32_t s5920_intcsr;
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uint32_t s5920_irqstate;
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CanBusState *canbus;
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};
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static void kvaser_pci_irq_handler(void *opaque, int irq_num, int level)
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{
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KvaserPCIState *d = (KvaserPCIState *)opaque;
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d->s5920_irqstate = level;
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if (d->s5920_intcsr & S5920_INTCSR_ADDON_INTENABLE_M) {
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pci_set_irq(&d->dev, level);
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}
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}
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static void kvaser_pci_reset(DeviceState *dev)
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{
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KvaserPCIState *d = KVASER_PCI_DEV(dev);
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CanSJA1000State *s = &d->sja_state;
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can_sja_hardware_reset(s);
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}
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static uint64_t kvaser_pci_s5920_io_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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KvaserPCIState *d = opaque;
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uint64_t val;
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switch (addr) {
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case S5920_INTCSR:
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val = d->s5920_intcsr;
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val &= ~S5920_INTCSR_INTERRUPT_ASSERTED_M;
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if (d->s5920_irqstate) {
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val |= S5920_INTCSR_INTERRUPT_ASSERTED_M;
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}
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return val;
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}
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return 0;
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}
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static void kvaser_pci_s5920_io_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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KvaserPCIState *d = opaque;
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switch (addr) {
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case S5920_INTCSR:
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if (d->s5920_irqstate &&
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((d->s5920_intcsr ^ data) & S5920_INTCSR_ADDON_INTENABLE_M)) {
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pci_set_irq(&d->dev, !!(data & S5920_INTCSR_ADDON_INTENABLE_M));
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}
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d->s5920_intcsr = data;
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break;
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}
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}
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static uint64_t kvaser_pci_sja_io_read(void *opaque, hwaddr addr, unsigned size)
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{
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KvaserPCIState *d = opaque;
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CanSJA1000State *s = &d->sja_state;
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if (addr >= KVASER_PCI_BYTES_PER_SJA) {
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return 0;
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}
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return can_sja_mem_read(s, addr, size);
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}
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static void kvaser_pci_sja_io_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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KvaserPCIState *d = opaque;
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CanSJA1000State *s = &d->sja_state;
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if (addr >= KVASER_PCI_BYTES_PER_SJA) {
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return;
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}
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can_sja_mem_write(s, addr, data, size);
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}
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static uint64_t kvaser_pci_xilinx_io_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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switch (addr) {
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case KVASER_PCI_XILINX_VERINT:
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return (KVASER_PCI_XILINX_VERSION_NUMBER << 4) | 0;
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}
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return 0;
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}
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static void kvaser_pci_xilinx_io_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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}
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static const MemoryRegionOps kvaser_pci_s5920_io_ops = {
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.read = kvaser_pci_s5920_io_read,
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.write = kvaser_pci_s5920_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps kvaser_pci_sja_io_ops = {
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.read = kvaser_pci_sja_io_read,
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.write = kvaser_pci_sja_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.max_access_size = 1,
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},
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};
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static const MemoryRegionOps kvaser_pci_xilinx_io_ops = {
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.read = kvaser_pci_xilinx_io_read,
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.write = kvaser_pci_xilinx_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.max_access_size = 1,
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},
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};
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static void kvaser_pci_realize(PCIDevice *pci_dev, Error **errp)
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{
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KvaserPCIState *d = KVASER_PCI_DEV(pci_dev);
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CanSJA1000State *s = &d->sja_state;
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uint8_t *pci_conf;
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pci_conf = pci_dev->config;
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pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
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d->irq = qemu_allocate_irq(kvaser_pci_irq_handler, d, 0);
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can_sja_init(s, d->irq);
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if (can_sja_connect_to_bus(s, d->canbus) < 0) {
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error_setg(errp, "can_sja_connect_to_bus failed");
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return;
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}
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memory_region_init_io(&d->s5920_io, OBJECT(d), &kvaser_pci_s5920_io_ops,
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d, "kvaser_pci-s5920", KVASER_PCI_S5920_RANGE);
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memory_region_init_io(&d->sja_io, OBJECT(d), &kvaser_pci_sja_io_ops,
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d, "kvaser_pci-sja", KVASER_PCI_SJA_RANGE);
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memory_region_init_io(&d->xilinx_io, OBJECT(d), &kvaser_pci_xilinx_io_ops,
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d, "kvaser_pci-xilinx", KVASER_PCI_XILINX_RANGE);
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pci_register_bar(&d->dev, /*BAR*/ 0, PCI_BASE_ADDRESS_SPACE_IO,
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&d->s5920_io);
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pci_register_bar(&d->dev, /*BAR*/ 1, PCI_BASE_ADDRESS_SPACE_IO,
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&d->sja_io);
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pci_register_bar(&d->dev, /*BAR*/ 2, PCI_BASE_ADDRESS_SPACE_IO,
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&d->xilinx_io);
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}
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static void kvaser_pci_exit(PCIDevice *pci_dev)
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{
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KvaserPCIState *d = KVASER_PCI_DEV(pci_dev);
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CanSJA1000State *s = &d->sja_state;
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can_sja_disconnect(s);
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qemu_free_irq(d->irq);
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}
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static const VMStateDescription vmstate_kvaser_pci = {
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.name = "kvaser_pci",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, KvaserPCIState),
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/* Load this before sja_state. */
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VMSTATE_UINT32(s5920_intcsr, KvaserPCIState),
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VMSTATE_STRUCT(sja_state, KvaserPCIState, 0, vmstate_can_sja,
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CanSJA1000State),
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VMSTATE_END_OF_LIST()
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}
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};
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static void kvaser_pci_instance_init(Object *obj)
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{
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KvaserPCIState *d = KVASER_PCI_DEV(obj);
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object_property_add_link(obj, "canbus", TYPE_CAN_BUS,
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(Object **)&d->canbus,
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qdev_prop_allow_set_link_before_realize,
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0);
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}
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static void kvaser_pci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = kvaser_pci_realize;
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k->exit = kvaser_pci_exit;
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k->vendor_id = KVASER_PCI_VENDOR_ID1;
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k->device_id = KVASER_PCI_DEVICE_ID1;
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k->revision = 0x00;
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k->class_id = 0x00ff00;
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dc->desc = "Kvaser PCICANx";
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dc->vmsd = &vmstate_kvaser_pci;
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dc->reset = kvaser_pci_reset;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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}
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static const TypeInfo kvaser_pci_info = {
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.name = TYPE_CAN_PCI_DEV,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(KvaserPCIState),
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.class_init = kvaser_pci_class_init,
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.instance_init = kvaser_pci_instance_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void kvaser_pci_register_types(void)
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{
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type_register_static(&kvaser_pci_info);
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}
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type_init(kvaser_pci_register_types)
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