b355f08a37
Currently we send VFP XML which includes D0..D15 or D0..D31, plus FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its definition of this XML feature does not include FPSID or FPEXC. In particular, for M-profile cores there are no FPSID or FPEXC registers, so advertising those is wrong. Move FPSID and FPEXC into their own bit of XML which we only send for A and R profile cores. This brings our definition of the XML org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for non-Neon cores...) and means we don't claim to have FPSID and FPEXC on M-profile. (It seems unlikely to me that any gdbstub users really care about being able to look at FPEXC and FPSID; but we've supplied them to gdb for a decade and it's not hard to keep doing so.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210921162901.17508-5-peter.maydell@linaro.org
44 lines
1.8 KiB
XML
44 lines
1.8 KiB
XML
<?xml version="1.0"?>
|
|
<!-- Copyright (C) 2008 Free Software Foundation, Inc.
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
are permitted in any medium without royalty provided the copyright
|
|
notice and this notice are preserved. -->
|
|
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
|
|
<feature name="org.gnu.gdb.arm.vfp">
|
|
<reg name="d0" bitsize="64" type="float"/>
|
|
<reg name="d1" bitsize="64" type="float"/>
|
|
<reg name="d2" bitsize="64" type="float"/>
|
|
<reg name="d3" bitsize="64" type="float"/>
|
|
<reg name="d4" bitsize="64" type="float"/>
|
|
<reg name="d5" bitsize="64" type="float"/>
|
|
<reg name="d6" bitsize="64" type="float"/>
|
|
<reg name="d7" bitsize="64" type="float"/>
|
|
<reg name="d8" bitsize="64" type="float"/>
|
|
<reg name="d9" bitsize="64" type="float"/>
|
|
<reg name="d10" bitsize="64" type="float"/>
|
|
<reg name="d11" bitsize="64" type="float"/>
|
|
<reg name="d12" bitsize="64" type="float"/>
|
|
<reg name="d13" bitsize="64" type="float"/>
|
|
<reg name="d14" bitsize="64" type="float"/>
|
|
<reg name="d15" bitsize="64" type="float"/>
|
|
<reg name="d16" bitsize="64" type="float"/>
|
|
<reg name="d17" bitsize="64" type="float"/>
|
|
<reg name="d18" bitsize="64" type="float"/>
|
|
<reg name="d19" bitsize="64" type="float"/>
|
|
<reg name="d20" bitsize="64" type="float"/>
|
|
<reg name="d21" bitsize="64" type="float"/>
|
|
<reg name="d22" bitsize="64" type="float"/>
|
|
<reg name="d23" bitsize="64" type="float"/>
|
|
<reg name="d24" bitsize="64" type="float"/>
|
|
<reg name="d25" bitsize="64" type="float"/>
|
|
<reg name="d26" bitsize="64" type="float"/>
|
|
<reg name="d27" bitsize="64" type="float"/>
|
|
<reg name="d28" bitsize="64" type="float"/>
|
|
<reg name="d29" bitsize="64" type="float"/>
|
|
<reg name="d30" bitsize="64" type="float"/>
|
|
<reg name="d31" bitsize="64" type="float"/>
|
|
|
|
<reg name="fpscr" bitsize="32" type="int" group="float"/>
|
|
</feature>
|