Peter Maydell cea66e9121 target-arm: Implement AArch64 TLBI operations on IPAs ... Implement the AArch64 TLBI operations which take an intermediate physical address and invalidate stage 2 translations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1439548879-1972-7-git-send-email-peter.maydell@linaro.org		2015-08-25 16:18:33 +01:00
..
arm_ldst.h
arm-semi.c
cpu64.c
cpu-qom.h	target-arm: Add the AArch64 view of the Secure physical timer	2015-08-13 11:26:22 +01:00
cpu.c	target-arm: Add the AArch64 view of the Secure physical timer	2015-08-13 11:26:22 +01:00
cpu.h	target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3	2015-08-25 15:45:08 +01:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c
helper-a64.h
helper.c	target-arm: Implement AArch64 TLBI operations on IPAs	2015-08-25 16:18:33 +01:00
helper.h
internals.h
iwmmxt_helper.c
kvm32.c	target-arm: kvm: Differentiate registers based on write-back levels	2015-07-21 11:18:45 +01:00
kvm64.c	target-arm: kvm: Differentiate registers based on write-back levels	2015-07-21 11:18:45 +01:00
kvm_arm.h	Introduce gic_class_name() instead of repeating condition	2015-08-13 11:26:21 +01:00
kvm-consts.h
kvm-stub.c	target-arm: kvm: Differentiate registers based on write-back levels	2015-07-21 11:18:45 +01:00
kvm.c	target-arm: kvm: Differentiate registers based on write-back levels	2015-07-21 11:18:45 +01:00
machine.c	target-arm: kvm: Differentiate registers based on write-back levels	2015-07-21 11:18:45 +01:00
Makefile.objs
neon_helper.c
op_addsub.h
op_helper.c	target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3	2015-08-25 15:45:08 +01:00
psci.c
translate-a64.c	tcg: Remove tcg_gen_trunc_i64_i32	2015-08-24 11:10:54 -07:00
translate.c	tcg: Remove tcg_gen_trunc_i64_i32	2015-08-24 11:10:54 -07:00
translate.h