1942 lines
61 KiB
C
1942 lines
61 KiB
C
/*
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* QEMU i8255x (PRO100) emulation
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*
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* Copyright (c) 2006-2007 Stefan Weil
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*
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* Portions of the code are copies from grub / etherboot eepro100.c
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* and linux e100.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Tested features (i82559):
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* PXE boot (i386) no valid link
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* Linux networking (i386) ok
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*
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* Untested:
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* non-i386 platforms
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* Windows networking
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*
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* References:
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*
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* Intel 8255x 10/100 Mbps Ethernet Controller Family
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* Open Source Software Developer Manual
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*/
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#if defined(TARGET_I386)
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# warning "PXE boot still not working!"
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#endif
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#include <stddef.h> /* offsetof */
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#include <stdbool.h>
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#include "hw.h"
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#include "pci.h"
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#include "net.h"
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#include "eeprom93xx.h"
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/* Common declarations for all PCI devices. */
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#define PCI_CONFIG_8(offset, value) \
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(pci_conf[offset] = (value))
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#define PCI_CONFIG_16(offset, value) \
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(*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
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#define PCI_CONFIG_32(offset, value) \
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(*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
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#define KiB 1024
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/* Debug EEPRO100 card. */
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//~ #define DEBUG_EEPRO100
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#ifdef DEBUG_EEPRO100
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#define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
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#else
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#define logout(fmt, ...) ((void)0)
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#endif
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/* Set flags to 0 to disable debug output. */
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#define INT 1 /* interrupt related actions */
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#define MDI 1 /* mdi related actions */
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#define OTHER 1
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#define RXTX 1
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#define EEPROM 1 /* eeprom related actions */
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#define TRACE(flag, command) ((flag) ? (command) : (void)0)
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#define missing(text) assert(!"feature is missing in this emulation: " text)
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#define MAX_ETH_FRAME_SIZE 1514
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/* This driver supports several different devices which are declared here. */
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#define i82550 0x82550
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#define i82551 0x82551
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#define i82557A 0x82557a
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#define i82557B 0x82557b
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#define i82557C 0x82557c
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#define i82558A 0x82558a
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#define i82558B 0x82558b
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#define i82559A 0x82559a
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#define i82559B 0x82559b
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#define i82559C 0x82559c
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#define i82559ER 0x82559e
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#define i82562 0x82562
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/* Use 64 word EEPROM. TODO: could be a runtime option. */
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#define EEPROM_SIZE 64
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#define PCI_MEM_SIZE (4 * KiB)
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#define PCI_IO_SIZE 64
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#define PCI_FLASH_SIZE (128 * KiB)
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#define BIT(n) (1 << (n))
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
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/* The SCB accepts the following controls for the Tx and Rx units: */
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#define CU_NOP 0x0000 /* No operation. */
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#define CU_START 0x0010 /* CU start. */
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#define CU_RESUME 0x0020 /* CU resume. */
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#define CU_STATSADDR 0x0040 /* Load dump counters address. */
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#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
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#define CU_CMD_BASE 0x0060 /* Load CU base address. */
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#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
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#define CU_SRESUME 0x00a0 /* CU static resume. */
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#define RU_NOP 0x0000
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#define RX_START 0x0001
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#define RX_RESUME 0x0002
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#define RX_ABORT 0x0004
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#define RX_ADDR_LOAD 0x0006
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#define RX_RESUMENR 0x0007
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#define INT_MASK 0x0100
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#define DRVR_INT 0x0200 /* Driver generated interrupt. */
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/* Offsets to the various registers.
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All accesses need not be longword aligned. */
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enum speedo_offsets {
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SCBStatus = 0,
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SCBAck = 1,
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SCBCmd = 2, /* Rx/Command Unit command and status. */
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SCBIntmask = 3,
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SCBPointer = 4, /* General purpose pointer. */
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SCBPort = 8, /* Misc. commands and operands. */
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SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
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SCBCtrlMDI = 16, /* MDI interface control. */
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SCBEarlyRx = 20, /* Early receive byte count. */
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SCBFlow = 24,
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};
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/* A speedo3 transmit buffer descriptor with two buffers... */
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typedef struct {
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uint16_t status;
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uint16_t command;
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uint32_t link; /* void * */
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uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
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uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
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uint8_t tx_threshold; /* transmit threshold */
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uint8_t tbd_count; /* TBD number */
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//~ /* This constitutes two "TBD" entries: hdr and data */
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//~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
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//~ int32_t tx_buf_size0; /* Length of Tx hdr. */
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//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
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//~ int32_t tx_buf_size1; /* Length of Tx data. */
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} eepro100_tx_t;
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/* Receive frame descriptor. */
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typedef struct {
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int16_t status;
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uint16_t command;
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uint32_t link; /* struct RxFD * */
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uint32_t rx_buf_addr; /* void * */
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uint16_t count;
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uint16_t size;
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char packet[MAX_ETH_FRAME_SIZE + 4];
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} eepro100_rx_t;
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typedef struct {
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uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
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tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
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tx_multiple_collisions, tx_total_collisions;
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uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
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rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
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rx_short_frame_errors;
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uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
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uint16_t xmt_tco_frames, rcv_tco_frames;
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uint32_t complete;
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} eepro100_stats_t;
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typedef enum {
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cu_idle = 0,
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cu_suspended = 1,
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cu_active = 2,
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cu_lpq_active = 2,
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cu_hqp_active = 3
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} cu_state_t;
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typedef enum {
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ru_idle = 0,
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ru_suspended = 1,
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ru_no_resources = 2,
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ru_ready = 4
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} ru_state_t;
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typedef struct {
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PCIDevice dev;
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#if 1
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uint8_t cmd;
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uint32_t start;
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uint32_t stop;
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uint8_t boundary;
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uint8_t tsr;
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uint8_t tpsr;
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uint16_t tcnt;
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uint16_t rcnt;
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uint32_t rsar;
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uint8_t rsr;
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uint8_t rxcr;
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uint8_t isr;
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uint8_t dcfg;
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uint8_t imr;
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uint8_t phys[6]; /* mac address */
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uint8_t curpag;
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uint8_t mult[8]; /* multicast mask array */
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int mmio_index;
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VLANClientState *vc;
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#endif
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uint8_t scb_stat; /* SCB stat/ack byte */
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uint8_t int_stat; /* PCI interrupt status */
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uint32_t region[3]; /* PCI region addresses */
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uint8_t macaddr[6];
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uint32_t statcounter[19];
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uint16_t mdimem[32];
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eeprom_t *eeprom;
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uint32_t device; /* device variant */
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uint32_t pointer;
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/* (cu_base + cu_offset) address the next command block in the command block list. */
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uint32_t cu_base; /* CU base address */
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uint32_t cu_offset; /* CU address offset */
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/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
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uint32_t ru_base; /* RU base address */
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uint32_t ru_offset; /* RU address offset */
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uint32_t statsaddr; /* pointer to eepro100_stats_t */
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eepro100_stats_t statistics; /* statistical counters */
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#if 0
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uint16_t status;
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#endif
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/* Configuration bytes. */
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uint8_t configuration[22];
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/* Data in mem is always in the byte order of the controller (le). */
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uint8_t mem[PCI_MEM_SIZE];
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} EEPRO100State;
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/* Default values for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_default[] = {
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/* MDI Registers 0 - 6, 7 */
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0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
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/* MDI Registers 8 - 15 */
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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/* MDI Registers 16 - 31 */
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0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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};
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/* Readonly mask for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_mask[] = {
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0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
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0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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};
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#define POLYNOMIAL 0x04c11db6
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/* From FreeBSD */
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/* XXX: optimize */
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static int compute_mcast_idx(const uint8_t * ep)
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{
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uint32_t crc;
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int carry, i, j;
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uint8_t b;
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crc = 0xffffffff;
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for (i = 0; i < 6; i++) {
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b = *ep++;
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for (j = 0; j < 8; j++) {
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
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crc <<= 1;
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b >>= 1;
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if (carry) {
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crc = ((crc ^ POLYNOMIAL) | carry);
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}
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}
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}
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return (crc >> 26);
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}
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#if defined(DEBUG_EEPRO100)
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static const char *nic_dump(const uint8_t * buf, unsigned size)
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{
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static char dump[3 * 16 + 1];
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char *p = &dump[0];
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if (size > 16) {
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size = 16;
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}
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while (size-- > 0) {
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p += sprintf(p, " %02x", *buf++);
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}
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return dump;
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}
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#endif /* DEBUG_EEPRO100 */
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enum scb_stat_ack {
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stat_ack_not_ours = 0x00,
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stat_ack_sw_gen = 0x04,
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stat_ack_rnr = 0x10,
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stat_ack_cu_idle = 0x20,
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stat_ack_frame_rx = 0x40,
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stat_ack_cu_cmd_done = 0x80,
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stat_ack_not_present = 0xFF,
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stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
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stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
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};
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static void disable_interrupt(EEPRO100State * s)
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{
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if (s->int_stat) {
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TRACE(INT, logout("interrupt disabled\n"));
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qemu_irq_lower(s->dev.irq[0]);
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s->int_stat = 0;
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}
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}
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static void enable_interrupt(EEPRO100State * s)
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{
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if (!s->int_stat) {
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TRACE(INT, logout("interrupt enabled\n"));
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qemu_irq_raise(s->dev.irq[0]);
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s->int_stat = 1;
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}
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}
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static void eepro100_acknowledge(EEPRO100State * s)
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{
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s->scb_stat &= ~s->mem[SCBAck];
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s->mem[SCBAck] = s->scb_stat;
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if (s->scb_stat == 0) {
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disable_interrupt(s);
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}
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}
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static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
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{
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uint8_t mask = ~s->mem[SCBIntmask];
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s->mem[SCBAck] |= stat;
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stat = s->scb_stat = s->mem[SCBAck];
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stat &= (mask | 0x0f);
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//~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
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if (stat && (mask & 0x01)) {
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/* SCB mask and SCB Bit M do not disable interrupt. */
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enable_interrupt(s);
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} else if (s->int_stat) {
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disable_interrupt(s);
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}
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}
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static void eepro100_cx_interrupt(EEPRO100State * s)
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{
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/* CU completed action command. */
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/* Transmit not ok (82557 only, not in emulation). */
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eepro100_interrupt(s, 0x80);
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}
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static void eepro100_cna_interrupt(EEPRO100State * s)
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{
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/* CU left the active state. */
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eepro100_interrupt(s, 0x20);
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}
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static void eepro100_fr_interrupt(EEPRO100State * s)
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{
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/* RU received a complete frame. */
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eepro100_interrupt(s, 0x40);
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}
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#if 0
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static void eepro100_rnr_interrupt(EEPRO100State * s)
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{
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/* RU is not ready. */
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eepro100_interrupt(s, 0x10);
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}
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#endif
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static void eepro100_mdi_interrupt(EEPRO100State * s)
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{
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/* MDI completed read or write cycle. */
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eepro100_interrupt(s, 0x08);
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}
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static void eepro100_swi_interrupt(EEPRO100State * s)
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{
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/* Software has requested an interrupt. */
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eepro100_interrupt(s, 0x04);
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}
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#if 0
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static void eepro100_fcp_interrupt(EEPRO100State * s)
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{
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/* Flow control pause interrupt (82558 and later). */
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eepro100_interrupt(s, 0x01);
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}
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#endif
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static void pci_reset(EEPRO100State * s)
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{
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uint32_t device = s->device;
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uint8_t *pci_conf = s->dev.config;
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TRACE(OTHER, logout("%p\n", s));
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/* PCI Vendor ID */
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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/* PCI Device ID depends on device and is set below. */
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/* PCI Command */
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PCI_CONFIG_16(PCI_COMMAND, 0x0000);
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/* PCI Status */
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PCI_CONFIG_16(PCI_STATUS, 0x2800);
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/* PCI Revision ID */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
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/* PCI Class Code */
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PCI_CONFIG_8(0x09, 0x00);
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pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
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/* PCI Cache Line Size */
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/* check cache line size!!! */
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//~ PCI_CONFIG_8(0x0c, 0x00);
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/* PCI Latency Timer */
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PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
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/* PCI Header Type */
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/* BIST (built-in self test) */
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#if defined(TARGET_I386)
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// !!! workaround for buggy bios
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//~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
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#endif
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#if 0
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/* PCI Base Address Registers */
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/* CSR Memory Mapped Base Address */
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PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
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PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH);
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/* CSR I/O Mapped Base Address */
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PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO);
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#if 0
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/* Flash Memory Mapped Base Address */
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PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM);
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#endif
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#endif
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/* Expansion ROM Base Address (depends on boot disable!!!) */
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PCI_CONFIG_32(0x30, 0x00000000);
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/* Capability Pointer */
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PCI_CONFIG_8(0x34, 0xdc);
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/* Interrupt Line */
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/* Interrupt Pin */
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PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
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/* Minimum Grant */
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PCI_CONFIG_8(0x3e, 0x08);
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/* Maximum Latency */
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PCI_CONFIG_8(0x3f, 0x18);
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/* Power Management Capabilities / Next Item Pointer / Capability ID */
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PCI_CONFIG_32(0xdc, 0x7e210001);
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switch (device) {
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case i82551:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
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break;
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case i82557B:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
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break;
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case i82557C:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
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break;
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case i82558B:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_16(PCI_STATUS, 0x2810);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
|
|
break;
|
|
case i82559C:
|
|
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
|
|
PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
|
//~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
|
break;
|
|
case i82559ER:
|
|
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
|
|
PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
|
PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
|
|
break;
|
|
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
|
|
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
|
|
default:
|
|
logout("Device %X is undefined!\n", device);
|
|
}
|
|
|
|
if (device == i82557C || device == i82558B || device == i82559C) {
|
|
logout("Get device id and revision from EEPROM!!!\n");
|
|
}
|
|
}
|
|
|
|
static void nic_selective_reset(EEPRO100State * s)
|
|
{
|
|
size_t i;
|
|
uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
|
|
//~ eeprom93xx_reset(s->eeprom);
|
|
memcpy(eeprom_contents, s->macaddr, 6);
|
|
eeprom_contents[0xa] = 0x4000;
|
|
uint16_t sum = 0;
|
|
for (i = 0; i < EEPROM_SIZE - 1; i++) {
|
|
sum += eeprom_contents[i];
|
|
}
|
|
eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
|
|
TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
|
|
|
|
memset(s->mem, 0, sizeof(s->mem));
|
|
uint32_t val = BIT(21);
|
|
memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
|
|
|
|
assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
|
|
memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
|
|
}
|
|
|
|
static void nic_reset(void *opaque)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
TRACE(OTHER, logout("%p\n", s));
|
|
nic_selective_reset(s);
|
|
}
|
|
|
|
#if defined(DEBUG_EEPRO100)
|
|
static const char * const reg[PCI_IO_SIZE / 4] = {
|
|
"Command/Status",
|
|
"General Pointer",
|
|
"Port",
|
|
"EEPROM/Flash Control",
|
|
"MDI Control",
|
|
"Receive DMA Byte Count",
|
|
"Flow control",
|
|
"General Status/Control"
|
|
};
|
|
|
|
static char *regname(uint32_t addr)
|
|
{
|
|
static char buf[16];
|
|
if (addr < PCI_IO_SIZE) {
|
|
const char *r = reg[addr / 4];
|
|
if (r != 0) {
|
|
snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
|
|
} else {
|
|
snprintf(buf, sizeof(buf), "0x%02x", addr);
|
|
}
|
|
} else {
|
|
snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
|
|
}
|
|
return buf;
|
|
}
|
|
#endif /* DEBUG_EEPRO100 */
|
|
|
|
#if 0
|
|
static uint16_t eepro100_read_status(EEPRO100State * s)
|
|
{
|
|
uint16_t val = s->status;
|
|
TRACE(OTHER, logout("val=0x%04x\n", val));
|
|
return val;
|
|
}
|
|
|
|
static void eepro100_write_status(EEPRO100State * s, uint16_t val)
|
|
{
|
|
TRACE(OTHER, logout("val=0x%04x\n", val));
|
|
s->status = val;
|
|
}
|
|
#endif
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* Command emulation.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#if 0
|
|
static uint16_t eepro100_read_command(EEPRO100State * s)
|
|
{
|
|
uint16_t val = 0xffff;
|
|
//~ TRACE(OTHER, logout("val=0x%04x\n", val));
|
|
return val;
|
|
}
|
|
#endif
|
|
|
|
static bool device_supports_eTxCB(EEPRO100State * s)
|
|
{
|
|
return (s->device != i82557B && s->device != i82557C);
|
|
}
|
|
|
|
/* Commands that can be put in a command list entry. */
|
|
enum commands {
|
|
CmdNOp = 0,
|
|
CmdIASetup = 1,
|
|
CmdConfigure = 2,
|
|
CmdMulticastList = 3,
|
|
CmdTx = 4,
|
|
CmdTDR = 5, /* load microcode */
|
|
CmdDump = 6,
|
|
CmdDiagnose = 7,
|
|
|
|
/* And some extra flags: */
|
|
CmdSuspend = 0x4000, /* Suspend after completion. */
|
|
CmdIntr = 0x2000, /* Interrupt after completion. */
|
|
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
|
|
};
|
|
|
|
static cu_state_t get_cu_state(EEPRO100State * s)
|
|
{
|
|
return ((s->mem[SCBStatus] >> 6) & 0x03);
|
|
}
|
|
|
|
static void set_cu_state(EEPRO100State * s, cu_state_t state)
|
|
{
|
|
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
|
|
}
|
|
|
|
static ru_state_t get_ru_state(EEPRO100State * s)
|
|
{
|
|
return ((s->mem[SCBStatus] >> 2) & 0x0f);
|
|
}
|
|
|
|
static void set_ru_state(EEPRO100State * s, ru_state_t state)
|
|
{
|
|
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
|
|
}
|
|
|
|
static void dump_statistics(EEPRO100State * s)
|
|
{
|
|
/* Dump statistical data. Most data is never changed by the emulation
|
|
* and always 0, so we first just copy the whole block and then those
|
|
* values which really matter.
|
|
* Number of data should check configuration!!!
|
|
*/
|
|
cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64);
|
|
stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
|
|
stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
|
|
stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
|
|
stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
|
|
//~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
|
|
//~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
|
|
//~ missing("CU dump statistical counters");
|
|
}
|
|
|
|
static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
|
|
{
|
|
eepro100_tx_t tx;
|
|
uint32_t cb_address;
|
|
switch (val) {
|
|
case CU_NOP:
|
|
/* No operation. */
|
|
break;
|
|
case CU_START:
|
|
if (get_cu_state(s) != cu_idle) {
|
|
/* Intel documentation says that CU must be idle for the CU
|
|
* start command. Intel driver for Linux also starts the CU
|
|
* from suspended state. */
|
|
logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
|
|
//~ assert(!"wrong CU state");
|
|
}
|
|
set_cu_state(s, cu_active);
|
|
s->cu_offset = s->pointer;
|
|
next_command:
|
|
cb_address = s->cu_base + s->cu_offset;
|
|
cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
|
|
uint16_t status = le16_to_cpu(tx.status);
|
|
uint16_t command = le16_to_cpu(tx.command);
|
|
logout
|
|
("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
|
|
val, status, command, tx.link);
|
|
bool bit_el = ((command & 0x8000) != 0);
|
|
bool bit_s = ((command & 0x4000) != 0);
|
|
bool bit_i = ((command & 0x2000) != 0);
|
|
bool bit_nc = ((command & 0x0010) != 0);
|
|
//~ bool bit_sf = ((command & 0x0008) != 0);
|
|
uint16_t cmd = command & 0x0007;
|
|
s->cu_offset = le32_to_cpu(tx.link);
|
|
switch (cmd) {
|
|
case CmdNOp:
|
|
/* Do nothing. */
|
|
break;
|
|
case CmdIASetup:
|
|
cpu_physical_memory_read(cb_address + 8, &s->macaddr[0], 6);
|
|
TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)));
|
|
break;
|
|
case CmdConfigure:
|
|
cpu_physical_memory_read(cb_address + 8, &s->configuration[0],
|
|
sizeof(s->configuration));
|
|
TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
|
|
break;
|
|
case CmdMulticastList:
|
|
//~ missing("multicast list");
|
|
break;
|
|
case CmdTx:
|
|
(void)0;
|
|
uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr);
|
|
uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
|
|
TRACE(RXTX, logout
|
|
("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
|
|
tbd_array, tcb_bytes, tx.tbd_count));
|
|
assert(!bit_nc);
|
|
//~ assert(!bit_sf);
|
|
assert(tcb_bytes <= 2600);
|
|
/* Next assertion fails for local configuration. */
|
|
//~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
|
|
if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
|
|
logout
|
|
("illegal values of TBD array address and TCB byte count!\n");
|
|
}
|
|
// sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
|
|
uint8_t buf[2600];
|
|
uint16_t size = 0;
|
|
uint32_t tbd_address = cb_address + 0x10;
|
|
assert(tcb_bytes <= sizeof(buf));
|
|
while (size < tcb_bytes) {
|
|
uint32_t tx_buffer_address = ldl_phys(tbd_address);
|
|
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
|
//~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
|
tbd_address += 8;
|
|
TRACE(RXTX, logout
|
|
("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
|
|
tx_buffer_address, tx_buffer_size));
|
|
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
|
cpu_physical_memory_read(tx_buffer_address, &buf[size],
|
|
tx_buffer_size);
|
|
size += tx_buffer_size;
|
|
}
|
|
if (tbd_array == 0xffffffff) {
|
|
/* Simplified mode. Was already handled by code above. */
|
|
} else {
|
|
/* Flexible mode. */
|
|
uint8_t tbd_count = 0;
|
|
if (device_supports_eTxCB(s) && !(s->configuration[6] & BIT(4))) {
|
|
/* Extended Flexible TCB. */
|
|
assert(tcb_bytes == 0);
|
|
for (; tbd_count < 2; tbd_count++) {
|
|
uint32_t tx_buffer_address = ldl_phys(tbd_address);
|
|
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
|
uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
|
tbd_address += 8;
|
|
TRACE(RXTX, logout
|
|
("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
|
tx_buffer_address, tx_buffer_size));
|
|
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
|
cpu_physical_memory_read(tx_buffer_address, &buf[size],
|
|
tx_buffer_size);
|
|
size += tx_buffer_size;
|
|
if (tx_buffer_el & 1) {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
tbd_address = tbd_array;
|
|
for (; tbd_count < tx.tbd_count; tbd_count++) {
|
|
uint32_t tx_buffer_address = ldl_phys(tbd_address);
|
|
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
|
uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
|
tbd_address += 8;
|
|
TRACE(RXTX, logout
|
|
("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
|
tx_buffer_address, tx_buffer_size));
|
|
tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
|
|
cpu_physical_memory_read(tx_buffer_address, &buf[size],
|
|
tx_buffer_size);
|
|
size += tx_buffer_size;
|
|
if (tx_buffer_el & 1) {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
|
|
qemu_send_packet(s->vc, buf, size);
|
|
s->statistics.tx_good_frames++;
|
|
/* Transmit with bad status would raise an CX/TNO interrupt.
|
|
* (82557 only). Emulation never has bad status. */
|
|
//~ eepro100_cx_interrupt(s);
|
|
break;
|
|
case CmdTDR:
|
|
TRACE(OTHER, logout("load microcode\n"));
|
|
/* Starting with offset 8, the command contains
|
|
* 64 dwords microcode which we just ignore here. */
|
|
break;
|
|
default:
|
|
missing("undefined command");
|
|
}
|
|
/* Write new status (success). */
|
|
stw_phys(cb_address, status | 0x8000 | 0x2000);
|
|
if (bit_i) {
|
|
/* CU completed action. */
|
|
eepro100_cx_interrupt(s);
|
|
}
|
|
if (bit_el) {
|
|
/* CU becomes idle. Terminate command loop. */
|
|
set_cu_state(s, cu_idle);
|
|
eepro100_cna_interrupt(s);
|
|
} else if (bit_s) {
|
|
/* CU becomes suspended. */
|
|
set_cu_state(s, cu_suspended);
|
|
eepro100_cna_interrupt(s);
|
|
} else {
|
|
/* More entries in list. */
|
|
TRACE(OTHER, logout("CU list with at least one more entry\n"));
|
|
goto next_command;
|
|
}
|
|
TRACE(OTHER, logout("CU list empty\n"));
|
|
/* List is empty. Now CU is idle or suspended. */
|
|
break;
|
|
case CU_RESUME:
|
|
if (get_cu_state(s) != cu_suspended) {
|
|
logout("bad CU resume from CU state %u\n", get_cu_state(s));
|
|
/* Workaround for bad Linux eepro100 driver which resumes
|
|
* from idle state. */
|
|
//~ missing("cu resume");
|
|
set_cu_state(s, cu_suspended);
|
|
}
|
|
if (get_cu_state(s) == cu_suspended) {
|
|
TRACE(OTHER, logout("CU resuming\n"));
|
|
set_cu_state(s, cu_active);
|
|
goto next_command;
|
|
}
|
|
break;
|
|
case CU_STATSADDR:
|
|
/* Load dump counters address. */
|
|
s->statsaddr = s->pointer;
|
|
TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
|
|
break;
|
|
case CU_SHOWSTATS:
|
|
/* Dump statistical counters. */
|
|
TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
|
|
dump_statistics(s);
|
|
break;
|
|
case CU_CMD_BASE:
|
|
/* Load CU base. */
|
|
TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
|
|
s->cu_base = s->pointer;
|
|
break;
|
|
case CU_DUMPSTATS:
|
|
/* Dump and reset statistical counters. */
|
|
TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
|
|
dump_statistics(s);
|
|
memset(&s->statistics, 0, sizeof(s->statistics));
|
|
break;
|
|
case CU_SRESUME:
|
|
/* CU static resume. */
|
|
missing("CU static resume");
|
|
break;
|
|
default:
|
|
missing("Undefined CU command");
|
|
}
|
|
}
|
|
|
|
static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
|
|
{
|
|
switch (val) {
|
|
case RU_NOP:
|
|
/* No operation. */
|
|
break;
|
|
case RX_START:
|
|
/* RU start. */
|
|
if (get_ru_state(s) != ru_idle) {
|
|
logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
|
|
//~ assert(!"wrong RU state");
|
|
}
|
|
set_ru_state(s, ru_ready);
|
|
s->ru_offset = s->pointer;
|
|
TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
|
|
break;
|
|
case RX_RESUME:
|
|
/* Restart RU. */
|
|
if (get_ru_state(s) != ru_suspended) {
|
|
logout("RU state is %u, should be %u\n", get_ru_state(s),
|
|
ru_suspended);
|
|
//~ assert(!"wrong RU state");
|
|
}
|
|
set_ru_state(s, ru_ready);
|
|
break;
|
|
case RX_ADDR_LOAD:
|
|
/* Load RU base. */
|
|
TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
|
|
s->ru_base = s->pointer;
|
|
break;
|
|
default:
|
|
logout("val=0x%02x (undefined RU command)\n", val);
|
|
missing("Undefined SU command");
|
|
}
|
|
}
|
|
|
|
static void eepro100_write_command(EEPRO100State * s, uint8_t val)
|
|
{
|
|
eepro100_ru_command(s, val & 0x0f);
|
|
eepro100_cu_command(s, val & 0xf0);
|
|
if ((val) == 0) {
|
|
TRACE(OTHER, logout("val=0x%02x\n", val));
|
|
}
|
|
/* Clear command byte after command was accepted. */
|
|
s->mem[SCBCmd] = 0;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* EEPROM emulation.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#define EEPROM_CS 0x02
|
|
#define EEPROM_SK 0x01
|
|
#define EEPROM_DI 0x04
|
|
#define EEPROM_DO 0x08
|
|
|
|
static uint16_t eepro100_read_eeprom(EEPRO100State * s)
|
|
{
|
|
uint16_t val;
|
|
memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
|
|
if (eeprom93xx_read(s->eeprom)) {
|
|
val |= EEPROM_DO;
|
|
} else {
|
|
val &= ~EEPROM_DO;
|
|
}
|
|
TRACE(EEPROM, logout("val=0x%04x\n", val));
|
|
return val;
|
|
}
|
|
|
|
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
|
|
{
|
|
TRACE(EEPROM, logout("val=0x%02x\n", val));
|
|
|
|
/* mask unwriteable bits */
|
|
//~ val = SET_MASKED(val, 0x31, eeprom->value);
|
|
|
|
int eecs = ((val & EEPROM_CS) != 0);
|
|
int eesk = ((val & EEPROM_SK) != 0);
|
|
int eedi = ((val & EEPROM_DI) != 0);
|
|
eeprom93xx_write(eeprom, eecs, eesk, eedi);
|
|
}
|
|
|
|
static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
|
|
{
|
|
s->pointer = le32_to_cpu(val);
|
|
TRACE(OTHER, logout("val=0x%08x\n", val));
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* MDI emulation.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#if defined(DEBUG_EEPRO100)
|
|
static const char * const mdi_op_name[] = {
|
|
"opcode 0",
|
|
"write",
|
|
"read",
|
|
"opcode 3"
|
|
};
|
|
|
|
static const char * const mdi_reg_name[] = {
|
|
"Control",
|
|
"Status",
|
|
"PHY Identification (Word 1)",
|
|
"PHY Identification (Word 2)",
|
|
"Auto-Negotiation Advertisement",
|
|
"Auto-Negotiation Link Partner Ability",
|
|
"Auto-Negotiation Expansion"
|
|
};
|
|
|
|
static const char *reg2name(uint8_t reg)
|
|
{
|
|
static char buffer[10];
|
|
const char *p = buffer;
|
|
if (reg < ARRAY_SIZE(mdi_reg_name)) {
|
|
p = mdi_reg_name[reg];
|
|
} else {
|
|
snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
|
|
}
|
|
return p;
|
|
}
|
|
#endif /* DEBUG_EEPRO100 */
|
|
|
|
static uint32_t eepro100_read_mdi(EEPRO100State * s)
|
|
{
|
|
uint32_t val;
|
|
memcpy(&val, &s->mem[0x10], sizeof(val));
|
|
|
|
#ifdef DEBUG_EEPRO100
|
|
uint8_t raiseint = (val & BIT(29)) >> 29;
|
|
uint8_t opcode = (val & BITS(27, 26)) >> 26;
|
|
uint8_t phy = (val & BITS(25, 21)) >> 21;
|
|
uint8_t reg = (val & BITS(20, 16)) >> 16;
|
|
uint16_t data = (val & BITS(15, 0));
|
|
#endif
|
|
/* Emulation takes no time to finish MDI transaction. */
|
|
val |= BIT(28);
|
|
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
|
val, raiseint, mdi_op_name[opcode], phy,
|
|
reg2name(reg), data));
|
|
return val;
|
|
}
|
|
|
|
static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
|
|
{
|
|
uint8_t raiseint = (val & BIT(29)) >> 29;
|
|
uint8_t opcode = (val & BITS(27, 26)) >> 26;
|
|
uint8_t phy = (val & BITS(25, 21)) >> 21;
|
|
uint8_t reg = (val & BITS(20, 16)) >> 16;
|
|
uint16_t data = (val & BITS(15, 0));
|
|
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
|
val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
|
|
if (phy != 1) {
|
|
/* Unsupported PHY address. */
|
|
//~ logout("phy must be 1 but is %u\n", phy);
|
|
data = 0;
|
|
} else if (opcode != 1 && opcode != 2) {
|
|
/* Unsupported opcode. */
|
|
logout("opcode must be 1 or 2 but is %u\n", opcode);
|
|
data = 0;
|
|
} else if (reg > 6) {
|
|
/* Unsupported register. */
|
|
logout("register must be 0...6 but is %u\n", reg);
|
|
data = 0;
|
|
} else {
|
|
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
|
val, raiseint, mdi_op_name[opcode], phy,
|
|
reg2name(reg), data));
|
|
if (opcode == 1) {
|
|
/* MDI write */
|
|
switch (reg) {
|
|
case 0: /* Control Register */
|
|
if (data & 0x8000) {
|
|
/* Reset status and control registers to default. */
|
|
s->mdimem[0] = eepro100_mdi_default[0];
|
|
s->mdimem[1] = eepro100_mdi_default[1];
|
|
data = s->mdimem[reg];
|
|
} else {
|
|
/* Restart Auto Configuration = Normal Operation */
|
|
data &= ~0x0200;
|
|
}
|
|
break;
|
|
case 1: /* Status Register */
|
|
missing("not writable");
|
|
data = s->mdimem[reg];
|
|
break;
|
|
case 2: /* PHY Identification Register (Word 1) */
|
|
case 3: /* PHY Identification Register (Word 2) */
|
|
missing("not implemented");
|
|
break;
|
|
case 4: /* Auto-Negotiation Advertisement Register */
|
|
case 5: /* Auto-Negotiation Link Partner Ability Register */
|
|
break;
|
|
case 6: /* Auto-Negotiation Expansion Register */
|
|
default:
|
|
missing("not implemented");
|
|
}
|
|
s->mdimem[reg] = data;
|
|
} else if (opcode == 2) {
|
|
/* MDI read */
|
|
switch (reg) {
|
|
case 0: /* Control Register */
|
|
if (data & 0x8000) {
|
|
/* Reset status and control registers to default. */
|
|
s->mdimem[0] = eepro100_mdi_default[0];
|
|
s->mdimem[1] = eepro100_mdi_default[1];
|
|
}
|
|
break;
|
|
case 1: /* Status Register */
|
|
s->mdimem[reg] |= 0x0020;
|
|
break;
|
|
case 2: /* PHY Identification Register (Word 1) */
|
|
case 3: /* PHY Identification Register (Word 2) */
|
|
case 4: /* Auto-Negotiation Advertisement Register */
|
|
break;
|
|
case 5: /* Auto-Negotiation Link Partner Ability Register */
|
|
s->mdimem[reg] = 0x41fe;
|
|
break;
|
|
case 6: /* Auto-Negotiation Expansion Register */
|
|
s->mdimem[reg] = 0x0001;
|
|
break;
|
|
}
|
|
data = s->mdimem[reg];
|
|
}
|
|
/* Emulation takes no time to finish MDI transaction.
|
|
* Set MDI bit in SCB status register. */
|
|
s->mem[SCBAck] |= 0x08;
|
|
val |= BIT(28);
|
|
if (raiseint) {
|
|
eepro100_mdi_interrupt(s);
|
|
}
|
|
}
|
|
val = (val & 0xffff0000) + data;
|
|
memcpy(&s->mem[0x10], &val, sizeof(val));
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* Port emulation.
|
|
*
|
|
****************************************************************************/
|
|
|
|
#define PORT_SOFTWARE_RESET 0
|
|
#define PORT_SELFTEST 1
|
|
#define PORT_SELECTIVE_RESET 2
|
|
#define PORT_DUMP 3
|
|
#define PORT_SELECTION_MASK 3
|
|
|
|
typedef struct {
|
|
uint32_t st_sign; /* Self Test Signature */
|
|
uint32_t st_result; /* Self Test Results */
|
|
} eepro100_selftest_t;
|
|
|
|
static uint32_t eepro100_read_port(EEPRO100State * s)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void eepro100_write_port(EEPRO100State * s, uint32_t val)
|
|
{
|
|
val = le32_to_cpu(val);
|
|
uint32_t address = (val & ~PORT_SELECTION_MASK);
|
|
uint8_t selection = (val & PORT_SELECTION_MASK);
|
|
switch (selection) {
|
|
case PORT_SOFTWARE_RESET:
|
|
nic_reset(s);
|
|
break;
|
|
case PORT_SELFTEST:
|
|
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
|
|
eepro100_selftest_t data;
|
|
cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
|
|
data.st_sign = 0xffffffff;
|
|
data.st_result = 0;
|
|
cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
|
|
break;
|
|
case PORT_SELECTIVE_RESET:
|
|
TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
|
|
nic_selective_reset(s);
|
|
break;
|
|
default:
|
|
logout("val=0x%08x\n", val);
|
|
missing("unknown port selection");
|
|
}
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* General hardware emulation.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
|
|
{
|
|
uint8_t val;
|
|
if (addr <= sizeof(s->mem) - sizeof(val)) {
|
|
memcpy(&val, &s->mem[addr], sizeof(val));
|
|
}
|
|
|
|
switch (addr) {
|
|
case SCBStatus:
|
|
//~ val = eepro100_read_status(s);
|
|
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
|
break;
|
|
case SCBAck:
|
|
//~ val = eepro100_read_status(s);
|
|
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
|
break;
|
|
case SCBCmd:
|
|
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
|
//~ val = eepro100_read_command(s);
|
|
break;
|
|
case SCBIntmask:
|
|
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
|
break;
|
|
case SCBPort + 3:
|
|
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
|
break;
|
|
case SCBeeprom:
|
|
val = eepro100_read_eeprom(s);
|
|
break;
|
|
case 0x1b: /* PMDR (power management driver register) */
|
|
val = 0;
|
|
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
|
break;
|
|
case 0x1d: /* general status register */
|
|
/* 100 Mbps full duplex, valid link */
|
|
val = 0x07;
|
|
TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
|
|
break;
|
|
default:
|
|
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
missing("unknown byte read");
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
|
|
{
|
|
uint16_t val;
|
|
if (addr <= sizeof(s->mem) - sizeof(val)) {
|
|
memcpy(&val, &s->mem[addr], sizeof(val));
|
|
}
|
|
|
|
switch (addr) {
|
|
case SCBStatus:
|
|
//~ val = eepro100_read_status(s);
|
|
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
|
break;
|
|
case SCBeeprom:
|
|
val = eepro100_read_eeprom(s);
|
|
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
|
break;
|
|
default:
|
|
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
|
missing("unknown word read");
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
|
|
{
|
|
uint32_t val;
|
|
if (addr <= sizeof(s->mem) - sizeof(val)) {
|
|
memcpy(&val, &s->mem[addr], sizeof(val));
|
|
}
|
|
|
|
switch (addr) {
|
|
case SCBStatus:
|
|
//~ val = eepro100_read_status(s);
|
|
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
|
break;
|
|
case SCBPointer:
|
|
//~ val = eepro100_read_pointer(s);
|
|
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
|
break;
|
|
case SCBPort:
|
|
val = eepro100_read_port(s);
|
|
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
|
break;
|
|
case SCBCtrlMDI:
|
|
val = eepro100_read_mdi(s);
|
|
break;
|
|
default:
|
|
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
|
missing("unknown longword read");
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
|
|
{
|
|
if (addr <= sizeof(s->mem) - sizeof(val)) {
|
|
memcpy(&s->mem[addr], &val, sizeof(val));
|
|
}
|
|
|
|
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
|
|
|
switch (addr) {
|
|
case SCBStatus:
|
|
//~ eepro100_write_status(s, val);
|
|
break;
|
|
case SCBAck:
|
|
eepro100_acknowledge(s);
|
|
break;
|
|
case SCBCmd:
|
|
eepro100_write_command(s, val);
|
|
break;
|
|
case SCBIntmask:
|
|
if (val & BIT(1)) {
|
|
eepro100_swi_interrupt(s);
|
|
}
|
|
eepro100_interrupt(s, 0);
|
|
break;
|
|
case SCBPort + 3:
|
|
case SCBFlow: /* does not exist on 82557 */
|
|
case SCBFlow + 1:
|
|
case SCBFlow + 2:
|
|
case SCBFlow + 3:
|
|
TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
|
|
break;
|
|
case SCBeeprom:
|
|
eepro100_write_eeprom(s->eeprom, val);
|
|
break;
|
|
default:
|
|
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
missing("unknown byte write");
|
|
}
|
|
}
|
|
|
|
static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
|
|
{
|
|
if (addr <= sizeof(s->mem) - sizeof(val)) {
|
|
memcpy(&s->mem[addr], &val, sizeof(val));
|
|
}
|
|
|
|
TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
|
|
|
|
switch (addr) {
|
|
case SCBStatus:
|
|
//~ eepro100_write_status(s, val);
|
|
eepro100_acknowledge(s);
|
|
break;
|
|
case SCBCmd:
|
|
eepro100_write_command(s, val);
|
|
eepro100_write1(s, SCBIntmask, val >> 8);
|
|
break;
|
|
case SCBeeprom:
|
|
eepro100_write_eeprom(s->eeprom, val);
|
|
break;
|
|
default:
|
|
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
|
missing("unknown word write");
|
|
}
|
|
}
|
|
|
|
static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
|
|
{
|
|
if (addr <= sizeof(s->mem) - sizeof(val)) {
|
|
memcpy(&s->mem[addr], &val, sizeof(val));
|
|
}
|
|
|
|
switch (addr) {
|
|
case SCBPointer:
|
|
eepro100_write_pointer(s, val);
|
|
break;
|
|
case SCBPort:
|
|
TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
|
|
eepro100_write_port(s, val);
|
|
break;
|
|
case SCBCtrlMDI:
|
|
eepro100_write_mdi(s, val);
|
|
break;
|
|
default:
|
|
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
|
missing("unknown longword write");
|
|
}
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* Port mapped I/O.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static uint32_t ioport_read1(void *opaque, uint32_t addr)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
//~ logout("addr=%s\n", regname(addr));
|
|
return eepro100_read1(s, addr - s->region[1]);
|
|
}
|
|
|
|
static uint32_t ioport_read2(void *opaque, uint32_t addr)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
return eepro100_read2(s, addr - s->region[1]);
|
|
}
|
|
|
|
static uint32_t ioport_read4(void *opaque, uint32_t addr)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
return eepro100_read4(s, addr - s->region[1]);
|
|
}
|
|
|
|
static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
eepro100_write1(s, addr - s->region[1], val);
|
|
}
|
|
|
|
static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
eepro100_write2(s, addr - s->region[1], val);
|
|
}
|
|
|
|
static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
eepro100_write4(s, addr - s->region[1], val);
|
|
}
|
|
|
|
/***********************************************************/
|
|
/* PCI EEPRO100 definitions */
|
|
|
|
static void pci_map(PCIDevice * pci_dev, int region_num,
|
|
uint32_t addr, uint32_t size, int type)
|
|
{
|
|
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
|
|
|
|
TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
|
|
region_num, addr, size, type));
|
|
|
|
assert(region_num == 1);
|
|
register_ioport_write(addr, size, 1, ioport_write1, s);
|
|
register_ioport_read(addr, size, 1, ioport_read1, s);
|
|
register_ioport_write(addr, size, 2, ioport_write2, s);
|
|
register_ioport_read(addr, size, 2, ioport_read2, s);
|
|
register_ioport_write(addr, size, 4, ioport_write4, s);
|
|
register_ioport_read(addr, size, 4, ioport_read4, s);
|
|
|
|
s->region[region_num] = addr;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
*
|
|
* Memory mapped I/O.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
eepro100_write1(s, addr, val);
|
|
}
|
|
|
|
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
eepro100_write2(s, addr, val);
|
|
}
|
|
|
|
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
|
eepro100_write4(s, addr, val);
|
|
}
|
|
|
|
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
//~ logout("addr=%s\n", regname(addr));
|
|
return eepro100_read1(s, addr);
|
|
}
|
|
|
|
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
//~ logout("addr=%s\n", regname(addr));
|
|
return eepro100_read2(s, addr);
|
|
}
|
|
|
|
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
//~ logout("addr=%s\n", regname(addr));
|
|
return eepro100_read4(s, addr);
|
|
}
|
|
|
|
static CPUWriteMemoryFunc * const pci_mmio_write[] = {
|
|
pci_mmio_writeb,
|
|
pci_mmio_writew,
|
|
pci_mmio_writel
|
|
};
|
|
|
|
static CPUReadMemoryFunc * const pci_mmio_read[] = {
|
|
pci_mmio_readb,
|
|
pci_mmio_readw,
|
|
pci_mmio_readl
|
|
};
|
|
|
|
static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
|
|
uint32_t addr, uint32_t size, int type)
|
|
{
|
|
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
|
|
|
|
TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
|
|
region_num, addr, size, type));
|
|
|
|
if (region_num == 0) {
|
|
/* Map control / status registers. */
|
|
cpu_register_physical_memory(addr, size, s->mmio_index);
|
|
s->region[region_num] = addr;
|
|
}
|
|
}
|
|
|
|
static int nic_can_receive(VLANClientState *vc)
|
|
{
|
|
EEPRO100State *s = vc->opaque;
|
|
TRACE(RXTX, logout("%p\n", s));
|
|
return get_ru_state(s) == ru_ready;
|
|
//~ return !eepro100_buffer_full(s);
|
|
}
|
|
|
|
static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size)
|
|
{
|
|
/* TODO:
|
|
* - Magic packets should set bit 30 in power management driver register.
|
|
* - Interesting packets should set bit 29 in power management driver register.
|
|
*/
|
|
EEPRO100State *s = vc->opaque;
|
|
uint16_t rfd_status = 0xa000;
|
|
static const uint8_t broadcast_macaddr[6] =
|
|
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
|
|
|
/* TODO: check multiple IA bit. */
|
|
assert(!(s->configuration[20] & BIT(6)));
|
|
|
|
if (s->configuration[8] & 0x80) {
|
|
/* CSMA is disabled. */
|
|
logout("%p received while CSMA is disabled\n", s);
|
|
return -1;
|
|
} else if (size < 64 && (s->configuration[7] & 1)) {
|
|
/* Short frame and configuration byte 7/0 (discard short receive) set:
|
|
* Short frame is discarded */
|
|
logout("%p received short frame (%zu byte)\n", s, size);
|
|
s->statistics.rx_short_frame_errors++;
|
|
//~ return -1;
|
|
} else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
|
|
/* Long frame and configuration byte 18/3 (long receive ok) not set:
|
|
* Long frames are discarded. */
|
|
logout("%p received long frame (%zu byte), ignored\n", s, size);
|
|
return -1;
|
|
} else if (memcmp(buf, s->macaddr, 6) == 0) { // !!!
|
|
/* Frame matches individual address. */
|
|
/* TODO: check configuration byte 15/4 (ignore U/L). */
|
|
TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
|
|
} else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
|
|
/* Broadcast frame. */
|
|
TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
|
|
rfd_status |= 0x0002;
|
|
} else if (buf[0] & 0x01) { // !!!
|
|
/* Multicast frame. */
|
|
TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size));
|
|
/* TODO: check multicast all bit. */
|
|
assert(!(s->configuration[21] & BIT(3)));
|
|
int mcast_idx = compute_mcast_idx(buf);
|
|
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
|
|
return size;
|
|
}
|
|
rfd_status |= 0x0002;
|
|
} else if (s->configuration[15] & 1) {
|
|
/* Promiscuous: receive all. */
|
|
TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
|
|
rfd_status |= 0x0004;
|
|
} else {
|
|
TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
|
|
nic_dump(buf, size)));
|
|
return size;
|
|
}
|
|
|
|
if (get_ru_state(s) != ru_ready) {
|
|
/* No resources available. */
|
|
logout("no resources, state=%u\n", get_ru_state(s));
|
|
s->statistics.rx_resource_errors++;
|
|
//~ assert(!"no resources");
|
|
return -1;
|
|
}
|
|
//~ !!!
|
|
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
|
|
eepro100_rx_t rx;
|
|
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
|
|
offsetof(eepro100_rx_t, packet));
|
|
uint16_t rfd_command = le16_to_cpu(rx.command);
|
|
uint16_t rfd_size = le16_to_cpu(rx.size);
|
|
assert(size <= rfd_size);
|
|
if (size < 64) {
|
|
rfd_status |= 0x0080;
|
|
}
|
|
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
|
|
rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
|
|
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
|
|
rfd_status);
|
|
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
|
|
/* Early receive interrupt not supported. */
|
|
//~ eepro100_er_interrupt(s);
|
|
/* Receive CRC Transfer not supported. */
|
|
assert(!(s->configuration[18] & 4));
|
|
/* TODO: check stripping enable bit. */
|
|
//~ assert(!(s->configuration[17] & 1));
|
|
cpu_physical_memory_write(s->ru_base + s->ru_offset +
|
|
offsetof(eepro100_rx_t, packet), buf, size);
|
|
s->statistics.rx_good_frames++;
|
|
eepro100_fr_interrupt(s);
|
|
s->ru_offset = le32_to_cpu(rx.link);
|
|
if (rfd_command & 0x8000) {
|
|
/* EL bit is set, so this was the last frame. */
|
|
assert(0);
|
|
}
|
|
if (rfd_command & 0x4000) {
|
|
/* S bit is set. */
|
|
set_ru_state(s, ru_suspended);
|
|
}
|
|
return size;
|
|
}
|
|
|
|
static int nic_load(QEMUFile * f, void *opaque, int version_id)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
int i;
|
|
int ret;
|
|
|
|
if (version_id > 3)
|
|
return -EINVAL;
|
|
|
|
if (version_id >= 3) {
|
|
ret = pci_device_load(&s->dev, f);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
if (version_id >= 2) {
|
|
qemu_get_8s(f, &s->rxcr);
|
|
} else {
|
|
s->rxcr = 0x0c;
|
|
}
|
|
|
|
qemu_get_8s(f, &s->cmd);
|
|
qemu_get_be32s(f, &s->start);
|
|
qemu_get_be32s(f, &s->stop);
|
|
qemu_get_8s(f, &s->boundary);
|
|
qemu_get_8s(f, &s->tsr);
|
|
qemu_get_8s(f, &s->tpsr);
|
|
qemu_get_be16s(f, &s->tcnt);
|
|
qemu_get_be16s(f, &s->rcnt);
|
|
qemu_get_be32s(f, &s->rsar);
|
|
qemu_get_8s(f, &s->rsr);
|
|
qemu_get_8s(f, &s->isr);
|
|
qemu_get_8s(f, &s->dcfg);
|
|
qemu_get_8s(f, &s->imr);
|
|
qemu_get_buffer(f, s->phys, 6);
|
|
qemu_get_8s(f, &s->curpag);
|
|
qemu_get_buffer(f, s->mult, 8);
|
|
qemu_get_buffer(f, s->mem, sizeof(s->mem));
|
|
|
|
/* Restore all members of struct between scv_stat and mem. */
|
|
qemu_get_8s(f, &s->scb_stat);
|
|
qemu_get_8s(f, &s->int_stat);
|
|
for (i = 0; i < 3; i++) {
|
|
qemu_get_be32s(f, &s->region[i]);
|
|
}
|
|
qemu_get_buffer(f, s->macaddr, 6);
|
|
for (i = 0; i < 19; i++) {
|
|
qemu_get_be32s(f, &s->statcounter[i]);
|
|
}
|
|
for (i = 0; i < 32; i++) {
|
|
qemu_get_be16s(f, &s->mdimem[i]);
|
|
}
|
|
/* The eeprom should be saved and restored by its own routines. */
|
|
qemu_get_be32s(f, &s->device);
|
|
qemu_get_be32s(f, &s->pointer);
|
|
qemu_get_be32s(f, &s->cu_base);
|
|
qemu_get_be32s(f, &s->cu_offset);
|
|
qemu_get_be32s(f, &s->ru_base);
|
|
qemu_get_be32s(f, &s->ru_offset);
|
|
qemu_get_be32s(f, &s->statsaddr);
|
|
/* Restore epro100_stats_t statistics. */
|
|
qemu_get_be32s(f, &s->statistics.tx_good_frames);
|
|
qemu_get_be32s(f, &s->statistics.tx_max_collisions);
|
|
qemu_get_be32s(f, &s->statistics.tx_late_collisions);
|
|
qemu_get_be32s(f, &s->statistics.tx_underruns);
|
|
qemu_get_be32s(f, &s->statistics.tx_lost_crs);
|
|
qemu_get_be32s(f, &s->statistics.tx_deferred);
|
|
qemu_get_be32s(f, &s->statistics.tx_single_collisions);
|
|
qemu_get_be32s(f, &s->statistics.tx_multiple_collisions);
|
|
qemu_get_be32s(f, &s->statistics.tx_total_collisions);
|
|
qemu_get_be32s(f, &s->statistics.rx_good_frames);
|
|
qemu_get_be32s(f, &s->statistics.rx_crc_errors);
|
|
qemu_get_be32s(f, &s->statistics.rx_alignment_errors);
|
|
qemu_get_be32s(f, &s->statistics.rx_resource_errors);
|
|
qemu_get_be32s(f, &s->statistics.rx_overrun_errors);
|
|
qemu_get_be32s(f, &s->statistics.rx_cdt_errors);
|
|
qemu_get_be32s(f, &s->statistics.rx_short_frame_errors);
|
|
qemu_get_be32s(f, &s->statistics.fc_xmt_pause);
|
|
qemu_get_be32s(f, &s->statistics.fc_rcv_pause);
|
|
qemu_get_be32s(f, &s->statistics.fc_rcv_unsupported);
|
|
qemu_get_be16s(f, &s->statistics.xmt_tco_frames);
|
|
qemu_get_be16s(f, &s->statistics.rcv_tco_frames);
|
|
qemu_get_be32s(f, &s->statistics.complete);
|
|
#if 0
|
|
qemu_get_be16s(f, &s->status);
|
|
#endif
|
|
|
|
/* Configuration bytes. */
|
|
qemu_get_buffer(f, s->configuration, sizeof(s->configuration));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void nic_save(QEMUFile * f, void *opaque)
|
|
{
|
|
EEPRO100State *s = opaque;
|
|
int i;
|
|
|
|
pci_device_save(&s->dev, f);
|
|
|
|
qemu_put_8s(f, &s->rxcr);
|
|
|
|
qemu_put_8s(f, &s->cmd);
|
|
qemu_put_be32s(f, &s->start);
|
|
qemu_put_be32s(f, &s->stop);
|
|
qemu_put_8s(f, &s->boundary);
|
|
qemu_put_8s(f, &s->tsr);
|
|
qemu_put_8s(f, &s->tpsr);
|
|
qemu_put_be16s(f, &s->tcnt);
|
|
qemu_put_be16s(f, &s->rcnt);
|
|
qemu_put_be32s(f, &s->rsar);
|
|
qemu_put_8s(f, &s->rsr);
|
|
qemu_put_8s(f, &s->isr);
|
|
qemu_put_8s(f, &s->dcfg);
|
|
qemu_put_8s(f, &s->imr);
|
|
qemu_put_buffer(f, s->phys, 6);
|
|
qemu_put_8s(f, &s->curpag);
|
|
qemu_put_buffer(f, s->mult, 8);
|
|
qemu_put_buffer(f, s->mem, sizeof(s->mem));
|
|
|
|
/* Save all members of struct between scv_stat and mem. */
|
|
qemu_put_8s(f, &s->scb_stat);
|
|
qemu_put_8s(f, &s->int_stat);
|
|
for (i = 0; i < 3; i++) {
|
|
qemu_put_be32s(f, &s->region[i]);
|
|
}
|
|
qemu_put_buffer(f, s->macaddr, 6);
|
|
for (i = 0; i < 19; i++) {
|
|
qemu_put_be32s(f, &s->statcounter[i]);
|
|
}
|
|
for (i = 0; i < 32; i++) {
|
|
qemu_put_be16s(f, &s->mdimem[i]);
|
|
}
|
|
/* The eeprom should be saved and restored by its own routines. */
|
|
qemu_put_be32s(f, &s->device);
|
|
qemu_put_be32s(f, &s->pointer);
|
|
qemu_put_be32s(f, &s->cu_base);
|
|
qemu_put_be32s(f, &s->cu_offset);
|
|
qemu_put_be32s(f, &s->ru_base);
|
|
qemu_put_be32s(f, &s->ru_offset);
|
|
qemu_put_be32s(f, &s->statsaddr);
|
|
/* Save epro100_stats_t statistics. */
|
|
qemu_put_be32s(f, &s->statistics.tx_good_frames);
|
|
qemu_put_be32s(f, &s->statistics.tx_max_collisions);
|
|
qemu_put_be32s(f, &s->statistics.tx_late_collisions);
|
|
qemu_put_be32s(f, &s->statistics.tx_underruns);
|
|
qemu_put_be32s(f, &s->statistics.tx_lost_crs);
|
|
qemu_put_be32s(f, &s->statistics.tx_deferred);
|
|
qemu_put_be32s(f, &s->statistics.tx_single_collisions);
|
|
qemu_put_be32s(f, &s->statistics.tx_multiple_collisions);
|
|
qemu_put_be32s(f, &s->statistics.tx_total_collisions);
|
|
qemu_put_be32s(f, &s->statistics.rx_good_frames);
|
|
qemu_put_be32s(f, &s->statistics.rx_crc_errors);
|
|
qemu_put_be32s(f, &s->statistics.rx_alignment_errors);
|
|
qemu_put_be32s(f, &s->statistics.rx_resource_errors);
|
|
qemu_put_be32s(f, &s->statistics.rx_overrun_errors);
|
|
qemu_put_be32s(f, &s->statistics.rx_cdt_errors);
|
|
qemu_put_be32s(f, &s->statistics.rx_short_frame_errors);
|
|
qemu_put_be32s(f, &s->statistics.fc_xmt_pause);
|
|
qemu_put_be32s(f, &s->statistics.fc_rcv_pause);
|
|
qemu_put_be32s(f, &s->statistics.fc_rcv_unsupported);
|
|
qemu_put_be16s(f, &s->statistics.xmt_tco_frames);
|
|
qemu_put_be16s(f, &s->statistics.rcv_tco_frames);
|
|
qemu_put_be32s(f, &s->statistics.complete);
|
|
#if 0
|
|
qemu_put_be16s(f, &s->status);
|
|
#endif
|
|
|
|
/* Configuration bytes. */
|
|
qemu_put_buffer(f, s->configuration, sizeof(s->configuration));
|
|
}
|
|
|
|
static void nic_cleanup(VLANClientState *vc)
|
|
{
|
|
EEPRO100State *s = vc->opaque;
|
|
|
|
unregister_savevm(vc->model, s);
|
|
|
|
eeprom93xx_free(s->eeprom);
|
|
}
|
|
|
|
static int pci_nic_uninit(PCIDevice *pci_dev)
|
|
{
|
|
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
|
|
|
|
cpu_unregister_io_memory(s->mmio_index);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int nic_init(PCIDevice *pci_dev, uint32_t device)
|
|
{
|
|
EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
|
|
|
|
TRACE(OTHER, logout("\n"));
|
|
|
|
s->dev.unregister = pci_nic_uninit;
|
|
|
|
s->device = device;
|
|
|
|
pci_reset(s);
|
|
|
|
/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
|
|
* i82559 and later support 64 or 256 word EEPROM. */
|
|
s->eeprom = eeprom93xx_new(EEPROM_SIZE);
|
|
|
|
/* Handler for memory-mapped I/O */
|
|
s->mmio_index =
|
|
cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
|
|
|
|
pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
|
|
PCI_ADDRESS_SPACE_MEM |
|
|
PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map);
|
|
pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO,
|
|
pci_map);
|
|
pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM,
|
|
pci_mmio_map);
|
|
|
|
qdev_get_macaddr(&s->dev.qdev, s->macaddr);
|
|
logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
|
|
assert(s->region[1] == 0);
|
|
|
|
nic_reset(s);
|
|
|
|
s->vc = qdev_get_vlan_client(&s->dev.qdev,
|
|
nic_can_receive, nic_receive, NULL,
|
|
nic_cleanup, s);
|
|
|
|
qemu_format_nic_info_str(s->vc, s->macaddr);
|
|
TRACE(OTHER, logout("%s\n", s->vc->info_str));
|
|
|
|
qemu_register_reset(nic_reset, s);
|
|
|
|
register_savevm(s->vc->model, -1, 3, nic_save, nic_load, s);
|
|
return 0;
|
|
}
|
|
|
|
static int pci_i82550_init(PCIDevice *pci_dev)
|
|
{
|
|
return nic_init(pci_dev, i82550);
|
|
}
|
|
|
|
static int pci_i82551_init(PCIDevice *pci_dev)
|
|
{
|
|
return nic_init(pci_dev, i82551);
|
|
}
|
|
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static int pci_i82557a_init(PCIDevice *pci_dev)
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{
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return nic_init(pci_dev, i82557A);
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}
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static int pci_i82557b_init(PCIDevice *pci_dev)
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{
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return nic_init(pci_dev, i82557B);
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}
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static int pci_i82557c_init(PCIDevice *pci_dev)
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{
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return nic_init(pci_dev, i82557C);
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}
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static int pci_i82558a_init(PCIDevice *pci_dev)
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{
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return nic_init(pci_dev, i82558A);
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}
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static int pci_i82558b_init(PCIDevice *pci_dev)
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{
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return nic_init(pci_dev, i82558B);
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}
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static int pci_i82559a_init(PCIDevice *pci_dev)
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{
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return nic_init(pci_dev, i82559A);
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}
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|
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static int pci_i82559b_init(PCIDevice *pci_dev)
|
|
{
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return nic_init(pci_dev, i82559B);
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}
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|
|
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static int pci_i82559c_init(PCIDevice *pci_dev)
|
|
{
|
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return nic_init(pci_dev, i82559C);
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}
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|
|
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static int pci_i82559er_init(PCIDevice *pci_dev)
|
|
{
|
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return nic_init(pci_dev, i82559ER);
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}
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|
|
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static int pci_i82562_init(PCIDevice *pci_dev)
|
|
{
|
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return nic_init(pci_dev, i82562);
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}
|
|
|
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static PCIDeviceInfo eepro100_info[] = {
|
|
{
|
|
.qdev.name = "i82550",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82550_init,
|
|
},{
|
|
.qdev.name = "i82551",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82551_init,
|
|
},{
|
|
.qdev.name = "i82557a",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82557a_init,
|
|
},{
|
|
.qdev.name = "i82557b",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82557b_init,
|
|
},{
|
|
.qdev.name = "i82557c",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82557c_init,
|
|
},{
|
|
.qdev.name = "i82558a",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82558a_init,
|
|
},{
|
|
.qdev.name = "i82558b",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82558b_init,
|
|
},{
|
|
.qdev.name = "i82559a",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82559a_init,
|
|
},{
|
|
.qdev.name = "i82559b",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82559b_init,
|
|
},{
|
|
.qdev.name = "i82559c",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82559c_init,
|
|
},{
|
|
.qdev.name = "i82559er",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82559er_init,
|
|
},{
|
|
.qdev.name = "i82562",
|
|
.qdev.size = sizeof(EEPRO100State),
|
|
.init = pci_i82562_init,
|
|
},{
|
|
/* end of list */
|
|
}
|
|
};
|
|
|
|
static void eepro100_register_devices(void)
|
|
{
|
|
pci_qdev_register_many(eepro100_info);
|
|
}
|
|
|
|
device_init(eepro100_register_devices)
|