2571a6427c
During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Message-ID: <20231031154000.18134-4-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34 lines
1.4 KiB
C
34 lines
1.4 KiB
C
/*
|
|
* RISC-V PMU header file.
|
|
*
|
|
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2 or later, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#include "cpu.h"
|
|
#include "qapi/error.h"
|
|
|
|
bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
|
|
uint32_t target_ctr);
|
|
bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env,
|
|
uint32_t target_ctr);
|
|
void riscv_pmu_timer_cb(void *priv);
|
|
void riscv_pmu_init(RISCVCPU *cpu, Error **errp);
|
|
int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
|
|
uint32_t ctr_idx);
|
|
int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
|
|
void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
|
|
int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
|
|
uint32_t ctr_idx);
|