432732b5e4
A9 gtimer includes global control field and number of per-cpu fields. But only per-cpu ones are migrated. This patch adds a subsection for global control field migration. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-id: 164422345976.2186660.1104517592452494510.stgit@pasha-ThinkPad-X280 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
399 lines
11 KiB
C
399 lines
11 KiB
C
/*
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* Global peripheral timer block for ARM A9MP
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*
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* (C) 2013 Xilinx Inc.
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*
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* Written by François LEGAL
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/timer/a9gtimer.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/timer.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/core/cpu.h"
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#ifndef A9_GTIMER_ERR_DEBUG
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#define A9_GTIMER_ERR_DEBUG 0
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#endif
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#define DB_PRINT_L(level, ...) do { \
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if (A9_GTIMER_ERR_DEBUG > (level)) { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} \
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} while (0)
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#define DB_PRINT(...) DB_PRINT_L(0, ## __VA_ARGS__)
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static inline int a9_gtimer_get_current_cpu(A9GTimerState *s)
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{
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if (current_cpu->cpu_index >= s->num_cpu) {
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hw_error("a9gtimer: num-cpu %d but this cpu is %d!\n",
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s->num_cpu, current_cpu->cpu_index);
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}
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return current_cpu->cpu_index;
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}
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static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s)
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{
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uint64_t prescale = extract32(s->control, R_CONTROL_PRESCALER_SHIFT,
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R_CONTROL_PRESCALER_LEN);
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return (prescale + 1) * 10;
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}
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static A9GTimerUpdate a9_gtimer_get_update(A9GTimerState *s)
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{
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A9GTimerUpdate ret;
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ret.now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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ret.new = s->ref_counter +
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(ret.now - s->cpu_ref_time) / a9_gtimer_get_conv(s);
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return ret;
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}
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static void a9_gtimer_update(A9GTimerState *s, bool sync)
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{
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A9GTimerUpdate update = a9_gtimer_get_update(s);
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int i;
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int64_t next_cdiff = 0;
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for (i = 0; i < s->num_cpu; ++i) {
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A9GTimerPerCPU *gtb = &s->per_cpu[i];
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int64_t cdiff = 0;
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if ((s->control & R_CONTROL_TIMER_ENABLE) &&
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(gtb->control & R_CONTROL_COMP_ENABLE)) {
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/* R2p0+, where the compare function is >= */
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if (gtb->compare < update.new) {
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DB_PRINT("Compare event happened for CPU %d\n", i);
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gtb->status = 1;
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if (gtb->control & R_CONTROL_AUTO_INCREMENT && gtb->inc) {
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uint64_t inc =
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QEMU_ALIGN_UP(update.new - gtb->compare, gtb->inc);
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DB_PRINT("Auto incrementing timer compare by %"
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PRId64 "\n", inc);
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gtb->compare += inc;
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}
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}
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cdiff = (int64_t)gtb->compare - (int64_t)update.new + 1;
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if (cdiff > 0 && (cdiff < next_cdiff || !next_cdiff)) {
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next_cdiff = cdiff;
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}
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}
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qemu_set_irq(gtb->irq,
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gtb->status && (gtb->control & R_CONTROL_IRQ_ENABLE));
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}
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timer_del(s->timer);
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if (next_cdiff) {
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DB_PRINT("scheduling qemu_timer to fire again in %"
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PRIx64 " cycles\n", next_cdiff);
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timer_mod(s->timer, update.now + next_cdiff * a9_gtimer_get_conv(s));
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}
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if (s->control & R_CONTROL_TIMER_ENABLE) {
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s->counter = update.new;
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}
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if (sync) {
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s->cpu_ref_time = update.now;
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s->ref_counter = s->counter;
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}
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}
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static void a9_gtimer_update_no_sync(void *opaque)
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{
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A9GTimerState *s = A9_GTIMER(opaque);
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a9_gtimer_update(s, false);
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}
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static uint64_t a9_gtimer_read(void *opaque, hwaddr addr, unsigned size)
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{
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A9GTimerPerCPU *gtb = (A9GTimerPerCPU *)opaque;
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A9GTimerState *s = gtb->parent;
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A9GTimerUpdate update;
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uint64_t ret = 0;
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int shift = 0;
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switch (addr) {
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case R_COUNTER_HI:
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shift = 32;
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/* fallthrough */
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case R_COUNTER_LO:
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update = a9_gtimer_get_update(s);
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ret = extract64(update.new, shift, 32);
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break;
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case R_CONTROL:
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ret = s->control | gtb->control;
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break;
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case R_INTERRUPT_STATUS:
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ret = gtb->status;
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break;
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case R_COMPARATOR_HI:
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shift = 32;
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/* fallthrough */
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case R_COMPARATOR_LO:
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ret = extract64(gtb->compare, shift, 32);
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break;
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case R_AUTO_INCREMENT:
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ret = gtb->inc;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "bad a9gtimer register: %x\n",
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(unsigned)addr);
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return 0;
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}
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DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, ret);
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return ret;
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}
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static void a9_gtimer_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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A9GTimerPerCPU *gtb = (A9GTimerPerCPU *)opaque;
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A9GTimerState *s = gtb->parent;
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int shift = 0;
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DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, value);
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switch (addr) {
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case R_COUNTER_HI:
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shift = 32;
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/* fallthrough */
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case R_COUNTER_LO:
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/*
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* Keep it simple - ARM docco explicitly says to disable timer before
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* modding it, so don't bother trying to do all the difficult on the fly
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* timer modifications - (if they even work in real hardware??).
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*/
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if (s->control & R_CONTROL_TIMER_ENABLE) {
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qemu_log_mask(LOG_GUEST_ERROR, "Cannot mod running ARM gtimer\n");
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return;
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}
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s->counter = deposit64(s->counter, shift, 32, value);
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return;
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case R_CONTROL:
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a9_gtimer_update(s, (value ^ s->control) & R_CONTROL_NEEDS_SYNC);
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gtb->control = value & R_CONTROL_BANKED;
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s->control = value & ~R_CONTROL_BANKED;
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break;
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case R_INTERRUPT_STATUS:
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a9_gtimer_update(s, false);
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gtb->status &= ~value;
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break;
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case R_COMPARATOR_HI:
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shift = 32;
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/* fallthrough */
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case R_COMPARATOR_LO:
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a9_gtimer_update(s, false);
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gtb->compare = deposit64(gtb->compare, shift, 32, value);
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break;
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case R_AUTO_INCREMENT:
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gtb->inc = value;
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return;
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default:
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return;
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}
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a9_gtimer_update(s, false);
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}
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/* Wrapper functions to implement the "read global timer for
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* the current CPU" memory regions.
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*/
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static uint64_t a9_gtimer_this_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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A9GTimerState *s = A9_GTIMER(opaque);
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int id = a9_gtimer_get_current_cpu(s);
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/* no \n so concatenates with message from read fn */
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DB_PRINT("CPU:%d:", id);
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return a9_gtimer_read(&s->per_cpu[id], addr, size);
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}
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static void a9_gtimer_this_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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A9GTimerState *s = A9_GTIMER(opaque);
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int id = a9_gtimer_get_current_cpu(s);
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/* no \n so concatenates with message from write fn */
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DB_PRINT("CPU:%d:", id);
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a9_gtimer_write(&s->per_cpu[id], addr, value, size);
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}
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static const MemoryRegionOps a9_gtimer_this_ops = {
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.read = a9_gtimer_this_read,
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.write = a9_gtimer_this_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const MemoryRegionOps a9_gtimer_ops = {
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.read = a9_gtimer_read,
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.write = a9_gtimer_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void a9_gtimer_reset(DeviceState *dev)
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{
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A9GTimerState *s = A9_GTIMER(dev);
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int i;
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s->counter = 0;
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s->control = 0;
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for (i = 0; i < s->num_cpu; i++) {
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A9GTimerPerCPU *gtb = &s->per_cpu[i];
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gtb->control = 0;
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gtb->status = 0;
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gtb->compare = 0;
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gtb->inc = 0;
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}
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a9_gtimer_update(s, false);
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}
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static void a9_gtimer_realize(DeviceState *dev, Error **errp)
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{
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A9GTimerState *s = A9_GTIMER(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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int i;
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if (s->num_cpu < 1 || s->num_cpu > A9_GTIMER_MAX_CPUS) {
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error_setg(errp, "%s: num-cpu must be between 1 and %d",
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__func__, A9_GTIMER_MAX_CPUS);
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return;
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}
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memory_region_init_io(&s->iomem, OBJECT(dev), &a9_gtimer_this_ops, s,
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"a9gtimer shared", 0x20);
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sysbus_init_mmio(sbd, &s->iomem);
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s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, a9_gtimer_update_no_sync, s);
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for (i = 0; i < s->num_cpu; i++) {
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A9GTimerPerCPU *gtb = &s->per_cpu[i];
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gtb->parent = s;
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sysbus_init_irq(sbd, >b->irq);
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memory_region_init_io(>b->iomem, OBJECT(dev), &a9_gtimer_ops, gtb,
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"a9gtimer per cpu", 0x20);
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sysbus_init_mmio(sbd, >b->iomem);
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}
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}
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static bool vmstate_a9_gtimer_control_needed(void *opaque)
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{
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A9GTimerState *s = opaque;
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return s->control != 0;
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}
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static const VMStateDescription vmstate_a9_gtimer_per_cpu = {
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.name = "arm.cortex-a9-global-timer.percpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(control, A9GTimerPerCPU),
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VMSTATE_UINT64(compare, A9GTimerPerCPU),
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VMSTATE_UINT32(status, A9GTimerPerCPU),
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VMSTATE_UINT32(inc, A9GTimerPerCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_a9_gtimer_control = {
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.name = "arm.cortex-a9-global-timer.control",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = vmstate_a9_gtimer_control_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(control, A9GTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_a9_gtimer = {
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.name = "arm.cortex-a9-global-timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_TIMER_PTR(timer, A9GTimerState),
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VMSTATE_UINT64(counter, A9GTimerState),
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VMSTATE_UINT64(ref_counter, A9GTimerState),
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VMSTATE_UINT64(cpu_ref_time, A9GTimerState),
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VMSTATE_STRUCT_VARRAY_UINT32(per_cpu, A9GTimerState, num_cpu,
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1, vmstate_a9_gtimer_per_cpu,
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A9GTimerPerCPU),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_a9_gtimer_control,
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NULL
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}
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};
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static Property a9_gtimer_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0),
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DEFINE_PROP_END_OF_LIST()
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};
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static void a9_gtimer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = a9_gtimer_realize;
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dc->vmsd = &vmstate_a9_gtimer;
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dc->reset = a9_gtimer_reset;
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device_class_set_props(dc, a9_gtimer_properties);
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}
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static const TypeInfo a9_gtimer_info = {
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.name = TYPE_A9_GTIMER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(A9GTimerState),
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.class_init = a9_gtimer_class_init,
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};
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static void a9_gtimer_register_types(void)
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{
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type_register_static(&a9_gtimer_info);
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}
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type_init(a9_gtimer_register_types)
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