fa92bd4af7
INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
272 lines
8.5 KiB
C
272 lines
8.5 KiB
C
/*
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* Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "qemu/host-utils.h"
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#include "exec/exec-all.h"
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void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
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{
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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cs->exception_index = excp;
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if (excp == EXCP_YIELD) {
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env->yield_needed = 0;
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}
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if (excp == EXCP_DEBUG) {
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env->exception_taken = 0;
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}
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cpu_loop_exit(cs);
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}
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void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
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{
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uint32_t vector;
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env->pc = pc;
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if (env->sregs[PS] & PS_EXCM) {
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if (env->config->ndepc) {
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env->sregs[DEPC] = pc;
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} else {
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env->sregs[EPC1] = pc;
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}
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vector = EXC_DOUBLE;
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} else {
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env->sregs[EPC1] = pc;
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vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
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}
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env->sregs[EXCCAUSE] = cause;
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env->sregs[PS] |= PS_EXCM;
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HELPER(exception)(env, vector);
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}
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void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
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uint32_t pc, uint32_t cause, uint32_t vaddr)
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{
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env->sregs[EXCVADDR] = vaddr;
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HELPER(exception_cause)(env, pc, cause);
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}
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void debug_exception_env(CPUXtensaState *env, uint32_t cause)
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{
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if (xtensa_get_cintlevel(env) < env->config->debug_level) {
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HELPER(debug_exception)(env, env->pc, cause);
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}
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}
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void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
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{
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unsigned level = env->config->debug_level;
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env->pc = pc;
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env->sregs[DEBUGCAUSE] = cause;
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env->sregs[EPC1 + level - 1] = pc;
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env->sregs[EPS2 + level - 2] = env->sregs[PS];
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env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
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(level << PS_INTLEVEL_SHIFT);
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HELPER(exception)(env, EXC_DEBUG);
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}
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#ifndef CONFIG_USER_ONLY
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void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
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{
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CPUState *cpu;
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env->pc = pc;
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env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
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(intlevel << PS_INTLEVEL_SHIFT);
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qemu_mutex_lock_iothread();
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check_interrupts(env);
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qemu_mutex_unlock_iothread();
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if (env->pending_irq_level) {
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cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
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return;
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}
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cpu = CPU(xtensa_env_get_cpu(env));
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cpu->halted = 1;
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HELPER(exception)(env, EXCP_HLT);
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}
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void HELPER(check_interrupts)(CPUXtensaState *env)
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{
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qemu_mutex_lock_iothread();
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check_interrupts(env);
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qemu_mutex_unlock_iothread();
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}
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void HELPER(intset)(CPUXtensaState *env, uint32_t v)
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{
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atomic_or(&env->sregs[INTSET],
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v & env->config->inttype_mask[INTTYPE_SOFTWARE]);
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}
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void HELPER(intclear)(CPUXtensaState *env, uint32_t v)
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{
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atomic_and(&env->sregs[INTSET],
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~(v & (env->config->inttype_mask[INTTYPE_SOFTWARE] |
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env->config->inttype_mask[INTTYPE_EDGE])));
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}
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static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
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{
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if (xtensa_option_enabled(env->config,
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XTENSA_OPTION_RELOCATABLE_VECTOR)) {
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return vector - env->config->vecbase + env->sregs[VECBASE];
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} else {
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return vector;
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}
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}
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/*!
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* Handle penging IRQ.
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* For the high priority interrupt jump to the corresponding interrupt vector.
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* For the level-1 interrupt convert it to either user, kernel or double
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* exception with the 'level-1 interrupt' exception cause.
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*/
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static void handle_interrupt(CPUXtensaState *env)
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{
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int level = env->pending_irq_level;
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if (level > xtensa_get_cintlevel(env) &&
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level <= env->config->nlevel &&
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(env->config->level_mask[level] &
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env->sregs[INTSET] &
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env->sregs[INTENABLE])) {
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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if (level > 1) {
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env->sregs[EPC1 + level - 1] = env->pc;
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env->sregs[EPS2 + level - 2] = env->sregs[PS];
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env->sregs[PS] =
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(env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
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env->pc = relocated_vector(env,
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env->config->interrupt_vector[level]);
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} else {
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env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
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if (env->sregs[PS] & PS_EXCM) {
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if (env->config->ndepc) {
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env->sregs[DEPC] = env->pc;
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} else {
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env->sregs[EPC1] = env->pc;
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}
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cs->exception_index = EXC_DOUBLE;
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} else {
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env->sregs[EPC1] = env->pc;
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cs->exception_index =
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(env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
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}
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env->sregs[PS] |= PS_EXCM;
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}
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env->exception_taken = 1;
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}
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}
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/* Called from cpu_handle_interrupt with BQL held */
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void xtensa_cpu_do_interrupt(CPUState *cs)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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if (cs->exception_index == EXC_IRQ) {
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qemu_log_mask(CPU_LOG_INT,
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"%s(EXC_IRQ) level = %d, cintlevel = %d, "
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"pc = %08x, a0 = %08x, ps = %08x, "
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"intset = %08x, intenable = %08x, "
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"ccount = %08x\n",
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__func__, env->pending_irq_level,
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xtensa_get_cintlevel(env),
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env->pc, env->regs[0], env->sregs[PS],
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env->sregs[INTSET], env->sregs[INTENABLE],
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env->sregs[CCOUNT]);
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handle_interrupt(env);
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}
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switch (cs->exception_index) {
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case EXC_WINDOW_OVERFLOW4:
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case EXC_WINDOW_UNDERFLOW4:
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case EXC_WINDOW_OVERFLOW8:
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case EXC_WINDOW_UNDERFLOW8:
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case EXC_WINDOW_OVERFLOW12:
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case EXC_WINDOW_UNDERFLOW12:
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case EXC_KERNEL:
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case EXC_USER:
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case EXC_DOUBLE:
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case EXC_DEBUG:
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qemu_log_mask(CPU_LOG_INT, "%s(%d) "
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"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
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__func__, cs->exception_index,
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env->pc, env->regs[0], env->sregs[PS],
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env->sregs[CCOUNT]);
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if (env->config->exception_vector[cs->exception_index]) {
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uint32_t vector;
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vector = env->config->exception_vector[cs->exception_index];
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env->pc = relocated_vector(env, vector);
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env->exception_taken = 1;
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} else {
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qemu_log_mask(CPU_LOG_INT,
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"%s(pc = %08x) bad exception_index: %d\n",
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__func__, env->pc, cs->exception_index);
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}
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break;
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case EXC_IRQ:
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break;
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default:
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qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
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__func__, env->pc, cs->exception_index);
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break;
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}
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check_interrupts(env);
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}
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#else
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void xtensa_cpu_do_interrupt(CPUState *cs)
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{
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}
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#endif
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bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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cs->exception_index = EXC_IRQ;
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xtensa_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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