1bba0dc932
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
1304 lines
41 KiB
C
1304 lines
41 KiB
C
/*
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* i386 helpers (without register variable usage)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "kvm.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu.h"
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#include "monitor.h"
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#endif
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//#define DEBUG_MMU
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/* NOTE: must be called outside the CPU execute loop */
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void cpu_state_reset(CPUState *env)
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{
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int i;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
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}
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memset(env, 0, offsetof(CPUX86State, breakpoints));
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tlb_flush(env, 1);
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env->old_exception = -1;
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/* init to reset state */
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#ifdef CONFIG_SOFTMMU
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env->hflags |= HF_SOFTMMU_MASK;
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#endif
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env->hflags2 |= HF2_GIF_MASK;
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cpu_x86_update_cr0(env, 0x60000010);
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env->a20_mask = ~0x0;
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env->smbase = 0x30000;
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env->idt.limit = 0xffff;
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env->gdt.limit = 0xffff;
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env->ldt.limit = 0xffff;
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env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
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env->tr.limit = 0xffff;
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env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
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cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
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DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
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DESC_R_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_A_MASK);
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env->eip = 0xfff0;
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env->regs[R_EDX] = env->cpuid_version;
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env->eflags = 0x2;
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/* FPU init */
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for(i = 0;i < 8; i++)
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env->fptags[i] = 1;
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env->fpuc = 0x37f;
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env->mxcsr = 0x1f80;
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env->pat = 0x0007040600070406ULL;
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env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
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memset(env->dr, 0, sizeof(env->dr));
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env->dr[6] = DR6_FIXED_1;
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env->dr[7] = DR7_FIXED_1;
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cpu_breakpoint_remove_all(env, BP_CPU);
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cpu_watchpoint_remove_all(env, BP_CPU);
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}
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void cpu_x86_close(CPUX86State *env)
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{
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g_free(env);
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}
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static void cpu_x86_version(CPUState *env, int *family, int *model)
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{
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int cpuver = env->cpuid_version;
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if (family == NULL || model == NULL) {
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return;
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}
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*family = (cpuver >> 8) & 0x0f;
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*model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0x0f);
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}
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/* Broadcast MCA signal for processor version 06H_EH and above */
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int cpu_x86_support_mca_broadcast(CPUState *env)
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{
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int family = 0;
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int model = 0;
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cpu_x86_version(env, &family, &model);
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if ((family == 6 && model >= 14) || family > 6) {
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return 1;
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}
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return 0;
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}
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/***********************************************************/
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/* x86 debug */
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static const char *cc_op_str[] = {
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"DYNAMIC",
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"EFLAGS",
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"MULB",
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"MULW",
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"MULL",
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"MULQ",
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"ADDB",
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"ADDW",
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"ADDL",
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"ADDQ",
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"ADCB",
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"ADCW",
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"ADCL",
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"ADCQ",
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"SUBB",
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"SUBW",
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"SUBL",
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"SUBQ",
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"SBBB",
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"SBBW",
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"SBBL",
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"SBBQ",
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"LOGICB",
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"LOGICW",
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"LOGICL",
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"LOGICQ",
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"INCB",
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"INCW",
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"INCL",
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"INCQ",
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"DECB",
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"DECW",
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"DECL",
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"DECQ",
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"SHLB",
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"SHLW",
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"SHLL",
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"SHLQ",
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"SARB",
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"SARW",
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"SARL",
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"SARQ",
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};
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static void
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cpu_x86_dump_seg_cache(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
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const char *name, struct SegmentCache *sc)
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{
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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cpu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
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sc->selector, sc->base, sc->limit, sc->flags & 0x00ffff00);
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} else
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#endif
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{
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cpu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
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(uint32_t)sc->base, sc->limit, sc->flags & 0x00ffff00);
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}
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if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
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goto done;
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cpu_fprintf(f, " DPL=%d ", (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
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if (sc->flags & DESC_S_MASK) {
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if (sc->flags & DESC_CS_MASK) {
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cpu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
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((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
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cpu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
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(sc->flags & DESC_R_MASK) ? 'R' : '-');
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} else {
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cpu_fprintf(f, (sc->flags & DESC_B_MASK) ? "DS " : "DS16");
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cpu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
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(sc->flags & DESC_W_MASK) ? 'W' : '-');
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}
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cpu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
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} else {
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static const char *sys_type_name[2][16] = {
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{ /* 32 bit mode */
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"Reserved", "TSS16-avl", "LDT", "TSS16-busy",
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"CallGate16", "TaskGate", "IntGate16", "TrapGate16",
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"Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
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"CallGate32", "Reserved", "IntGate32", "TrapGate32"
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},
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{ /* 64 bit mode */
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"<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
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"Reserved", "Reserved", "Reserved", "Reserved",
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"TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
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"Reserved", "IntGate64", "TrapGate64"
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}
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};
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cpu_fprintf(f, "%s",
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sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
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[(sc->flags & DESC_TYPE_MASK)
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>> DESC_TYPE_SHIFT]);
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}
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done:
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cpu_fprintf(f, "\n");
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}
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#define DUMP_CODE_BYTES_TOTAL 50
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#define DUMP_CODE_BYTES_BACKWARD 20
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void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
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int flags)
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{
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int eflags, i, nb;
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char cc_op_name[32];
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static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
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cpu_synchronize_state(env);
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eflags = env->eflags;
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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cpu_fprintf(f,
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"RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
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"RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
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"R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
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"R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
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"RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
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env->regs[R_EAX],
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env->regs[R_EBX],
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env->regs[R_ECX],
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env->regs[R_EDX],
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env->regs[R_ESI],
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env->regs[R_EDI],
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env->regs[R_EBP],
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env->regs[R_ESP],
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env->regs[8],
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env->regs[9],
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env->regs[10],
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env->regs[11],
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env->regs[12],
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env->regs[13],
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env->regs[14],
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env->regs[15],
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env->eip, eflags,
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->hflags & HF_CPL_MASK,
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1,
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(env->hflags >> HF_SMM_SHIFT) & 1,
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env->halted);
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} else
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#endif
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{
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cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
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"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
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"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
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(uint32_t)env->regs[R_EAX],
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(uint32_t)env->regs[R_EBX],
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(uint32_t)env->regs[R_ECX],
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(uint32_t)env->regs[R_EDX],
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(uint32_t)env->regs[R_ESI],
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(uint32_t)env->regs[R_EDI],
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(uint32_t)env->regs[R_EBP],
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(uint32_t)env->regs[R_ESP],
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(uint32_t)env->eip, eflags,
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->hflags & HF_CPL_MASK,
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1,
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(env->hflags >> HF_SMM_SHIFT) & 1,
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env->halted);
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}
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for(i = 0; i < 6; i++) {
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cpu_x86_dump_seg_cache(env, f, cpu_fprintf, seg_name[i],
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&env->segs[i]);
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}
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cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "LDT", &env->ldt);
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cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR", &env->tr);
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
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env->gdt.base, env->gdt.limit);
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cpu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
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env->idt.base, env->idt.limit);
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cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
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(uint32_t)env->cr[0],
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env->cr[2],
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env->cr[3],
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(uint32_t)env->cr[4]);
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for(i = 0; i < 4; i++)
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cpu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
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cpu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
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env->dr[6], env->dr[7]);
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} else
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#endif
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{
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cpu_fprintf(f, "GDT= %08x %08x\n",
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(uint32_t)env->gdt.base, env->gdt.limit);
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cpu_fprintf(f, "IDT= %08x %08x\n",
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(uint32_t)env->idt.base, env->idt.limit);
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cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
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(uint32_t)env->cr[0],
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(uint32_t)env->cr[2],
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(uint32_t)env->cr[3],
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(uint32_t)env->cr[4]);
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for(i = 0; i < 4; i++) {
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cpu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
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}
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cpu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
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env->dr[6], env->dr[7]);
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}
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if (flags & X86_DUMP_CCOP) {
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if ((unsigned)env->cc_op < CC_OP_NB)
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snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
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else
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snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
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env->cc_src, env->cc_dst,
|
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cc_op_name);
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} else
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#endif
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{
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cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
|
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(uint32_t)env->cc_src, (uint32_t)env->cc_dst,
|
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cc_op_name);
|
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}
|
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}
|
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cpu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
|
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if (flags & X86_DUMP_FPU) {
|
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int fptag;
|
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fptag = 0;
|
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for(i = 0; i < 8; i++) {
|
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fptag |= ((!env->fptags[i]) << i);
|
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}
|
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cpu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
|
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env->fpuc,
|
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(env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
|
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env->fpstt,
|
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fptag,
|
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env->mxcsr);
|
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for(i=0;i<8;i++) {
|
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CPU_LDoubleU u;
|
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u.d = env->fpregs[i].d;
|
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cpu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
|
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i, u.l.lower, u.l.upper);
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if ((i & 1) == 1)
|
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cpu_fprintf(f, "\n");
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else
|
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cpu_fprintf(f, " ");
|
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}
|
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if (env->hflags & HF_CS64_MASK)
|
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nb = 16;
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else
|
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nb = 8;
|
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for(i=0;i<nb;i++) {
|
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cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
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i,
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env->xmm_regs[i].XMM_L(3),
|
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env->xmm_regs[i].XMM_L(2),
|
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env->xmm_regs[i].XMM_L(1),
|
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env->xmm_regs[i].XMM_L(0));
|
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if ((i & 1) == 1)
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cpu_fprintf(f, "\n");
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else
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cpu_fprintf(f, " ");
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}
|
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}
|
|
if (flags & CPU_DUMP_CODE) {
|
|
target_ulong base = env->segs[R_CS].base + env->eip;
|
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target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
|
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uint8_t code;
|
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char codestr[3];
|
|
|
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cpu_fprintf(f, "Code=");
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for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
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if (cpu_memory_rw_debug(env, base - offs + i, &code, 1, 0) == 0) {
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snprintf(codestr, sizeof(codestr), "%02x", code);
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} else {
|
|
snprintf(codestr, sizeof(codestr), "??");
|
|
}
|
|
cpu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
|
|
i == offs ? "<" : "", codestr, i == offs ? ">" : "");
|
|
}
|
|
cpu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
|
|
/***********************************************************/
|
|
/* x86 mmu */
|
|
/* XXX: add PGE support */
|
|
|
|
void cpu_x86_set_a20(CPUX86State *env, int a20_state)
|
|
{
|
|
a20_state = (a20_state != 0);
|
|
if (a20_state != ((env->a20_mask >> 20) & 1)) {
|
|
#if defined(DEBUG_MMU)
|
|
printf("A20 update: a20=%d\n", a20_state);
|
|
#endif
|
|
/* if the cpu is currently executing code, we must unlink it and
|
|
all the potentially executing TB */
|
|
cpu_interrupt(env, CPU_INTERRUPT_EXITTB);
|
|
|
|
/* when a20 is changed, all the MMU mappings are invalid, so
|
|
we must flush everything */
|
|
tlb_flush(env, 1);
|
|
env->a20_mask = ~(1 << 20) | (a20_state << 20);
|
|
}
|
|
}
|
|
|
|
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
|
|
{
|
|
int pe_state;
|
|
|
|
#if defined(DEBUG_MMU)
|
|
printf("CR0 update: CR0=0x%08x\n", new_cr0);
|
|
#endif
|
|
if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
|
|
(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
|
|
tlb_flush(env, 1);
|
|
}
|
|
|
|
#ifdef TARGET_X86_64
|
|
if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
|
|
(env->efer & MSR_EFER_LME)) {
|
|
/* enter in long mode */
|
|
/* XXX: generate an exception */
|
|
if (!(env->cr[4] & CR4_PAE_MASK))
|
|
return;
|
|
env->efer |= MSR_EFER_LMA;
|
|
env->hflags |= HF_LMA_MASK;
|
|
} else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
|
|
(env->efer & MSR_EFER_LMA)) {
|
|
/* exit long mode */
|
|
env->efer &= ~MSR_EFER_LMA;
|
|
env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
|
|
env->eip &= 0xffffffff;
|
|
}
|
|
#endif
|
|
env->cr[0] = new_cr0 | CR0_ET_MASK;
|
|
|
|
/* update PE flag in hidden flags */
|
|
pe_state = (env->cr[0] & CR0_PE_MASK);
|
|
env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
|
|
/* ensure that ADDSEG is always set in real mode */
|
|
env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
|
|
/* update FPU flags */
|
|
env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
|
|
((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
|
|
}
|
|
|
|
/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
|
|
the PDPT */
|
|
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
|
|
{
|
|
env->cr[3] = new_cr3;
|
|
if (env->cr[0] & CR0_PG_MASK) {
|
|
#if defined(DEBUG_MMU)
|
|
printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
|
|
#endif
|
|
tlb_flush(env, 0);
|
|
}
|
|
}
|
|
|
|
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
|
|
{
|
|
#if defined(DEBUG_MMU)
|
|
printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
|
|
#endif
|
|
if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
|
|
(env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
|
|
tlb_flush(env, 1);
|
|
}
|
|
/* SSE handling */
|
|
if (!(env->cpuid_features & CPUID_SSE))
|
|
new_cr4 &= ~CR4_OSFXSR_MASK;
|
|
if (new_cr4 & CR4_OSFXSR_MASK)
|
|
env->hflags |= HF_OSFXSR_MASK;
|
|
else
|
|
env->hflags &= ~HF_OSFXSR_MASK;
|
|
|
|
env->cr[4] = new_cr4;
|
|
}
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
|
|
int is_write, int mmu_idx)
|
|
{
|
|
/* user mode only emulation */
|
|
is_write &= 1;
|
|
env->cr[2] = addr;
|
|
env->error_code = (is_write << PG_ERROR_W_BIT);
|
|
env->error_code |= PG_ERROR_U_MASK;
|
|
env->exception_index = EXCP0E_PAGE;
|
|
return 1;
|
|
}
|
|
|
|
#else
|
|
|
|
/* XXX: This value should match the one returned by CPUID
|
|
* and in exec.c */
|
|
# if defined(TARGET_X86_64)
|
|
# define PHYS_ADDR_MASK 0xfffffff000LL
|
|
# else
|
|
# define PHYS_ADDR_MASK 0xffffff000LL
|
|
# endif
|
|
|
|
/* return value:
|
|
-1 = cannot handle fault
|
|
0 = nothing more to do
|
|
1 = generate PF fault
|
|
*/
|
|
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
|
|
int is_write1, int mmu_idx)
|
|
{
|
|
uint64_t ptep, pte;
|
|
target_ulong pde_addr, pte_addr;
|
|
int error_code, is_dirty, prot, page_size, is_write, is_user;
|
|
target_phys_addr_t paddr;
|
|
uint32_t page_offset;
|
|
target_ulong vaddr, virt_addr;
|
|
|
|
is_user = mmu_idx == MMU_USER_IDX;
|
|
#if defined(DEBUG_MMU)
|
|
printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
|
|
addr, is_write1, is_user, env->eip);
|
|
#endif
|
|
is_write = is_write1 & 1;
|
|
|
|
if (!(env->cr[0] & CR0_PG_MASK)) {
|
|
pte = addr;
|
|
virt_addr = addr & TARGET_PAGE_MASK;
|
|
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
|
page_size = 4096;
|
|
goto do_mapping;
|
|
}
|
|
|
|
if (env->cr[4] & CR4_PAE_MASK) {
|
|
uint64_t pde, pdpe;
|
|
target_ulong pdpe_addr;
|
|
|
|
#ifdef TARGET_X86_64
|
|
if (env->hflags & HF_LMA_MASK) {
|
|
uint64_t pml4e_addr, pml4e;
|
|
int32_t sext;
|
|
|
|
/* test virtual address sign extension */
|
|
sext = (int64_t)addr >> 47;
|
|
if (sext != 0 && sext != -1) {
|
|
env->error_code = 0;
|
|
env->exception_index = EXCP0D_GPF;
|
|
return 1;
|
|
}
|
|
|
|
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pml4e = ldq_phys(pml4e_addr);
|
|
if (!(pml4e & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
if (!(env->efer & MSR_EFER_NXE) && (pml4e & PG_NX_MASK)) {
|
|
error_code = PG_ERROR_RSVD_MASK;
|
|
goto do_fault;
|
|
}
|
|
if (!(pml4e & PG_ACCESSED_MASK)) {
|
|
pml4e |= PG_ACCESSED_MASK;
|
|
stl_phys_notdirty(pml4e_addr, pml4e);
|
|
}
|
|
ptep = pml4e ^ PG_NX_MASK;
|
|
pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pdpe = ldq_phys(pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
if (!(env->efer & MSR_EFER_NXE) && (pdpe & PG_NX_MASK)) {
|
|
error_code = PG_ERROR_RSVD_MASK;
|
|
goto do_fault;
|
|
}
|
|
ptep &= pdpe ^ PG_NX_MASK;
|
|
if (!(pdpe & PG_ACCESSED_MASK)) {
|
|
pdpe |= PG_ACCESSED_MASK;
|
|
stl_phys_notdirty(pdpe_addr, pdpe);
|
|
}
|
|
} else
|
|
#endif
|
|
{
|
|
/* XXX: load them when cr3 is loaded ? */
|
|
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
|
|
env->a20_mask;
|
|
pdpe = ldq_phys(pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
|
|
}
|
|
|
|
pde_addr = ((pdpe & PHYS_ADDR_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pde = ldq_phys(pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
if (!(env->efer & MSR_EFER_NXE) && (pde & PG_NX_MASK)) {
|
|
error_code = PG_ERROR_RSVD_MASK;
|
|
goto do_fault;
|
|
}
|
|
ptep &= pde ^ PG_NX_MASK;
|
|
if (pde & PG_PSE_MASK) {
|
|
/* 2 MB page */
|
|
page_size = 2048 * 1024;
|
|
ptep ^= PG_NX_MASK;
|
|
if ((ptep & PG_NX_MASK) && is_write1 == 2)
|
|
goto do_fault_protect;
|
|
if (is_user) {
|
|
if (!(ptep & PG_USER_MASK))
|
|
goto do_fault_protect;
|
|
if (is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
} else {
|
|
if ((env->cr[0] & CR0_WP_MASK) &&
|
|
is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
}
|
|
is_dirty = is_write && !(pde & PG_DIRTY_MASK);
|
|
if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
if (is_dirty)
|
|
pde |= PG_DIRTY_MASK;
|
|
stl_phys_notdirty(pde_addr, pde);
|
|
}
|
|
/* align to page_size */
|
|
pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
|
|
virt_addr = addr & ~(page_size - 1);
|
|
} else {
|
|
/* 4 KB page */
|
|
if (!(pde & PG_ACCESSED_MASK)) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
stl_phys_notdirty(pde_addr, pde);
|
|
}
|
|
pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pte = ldq_phys(pte_addr);
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
if (!(env->efer & MSR_EFER_NXE) && (pte & PG_NX_MASK)) {
|
|
error_code = PG_ERROR_RSVD_MASK;
|
|
goto do_fault;
|
|
}
|
|
/* combine pde and pte nx, user and rw protections */
|
|
ptep &= pte ^ PG_NX_MASK;
|
|
ptep ^= PG_NX_MASK;
|
|
if ((ptep & PG_NX_MASK) && is_write1 == 2)
|
|
goto do_fault_protect;
|
|
if (is_user) {
|
|
if (!(ptep & PG_USER_MASK))
|
|
goto do_fault_protect;
|
|
if (is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
} else {
|
|
if ((env->cr[0] & CR0_WP_MASK) &&
|
|
is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
}
|
|
is_dirty = is_write && !(pte & PG_DIRTY_MASK);
|
|
if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
|
|
pte |= PG_ACCESSED_MASK;
|
|
if (is_dirty)
|
|
pte |= PG_DIRTY_MASK;
|
|
stl_phys_notdirty(pte_addr, pte);
|
|
}
|
|
page_size = 4096;
|
|
virt_addr = addr & ~0xfff;
|
|
pte = pte & (PHYS_ADDR_MASK | 0xfff);
|
|
}
|
|
} else {
|
|
uint32_t pde;
|
|
|
|
/* page directory entry */
|
|
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
|
|
env->a20_mask;
|
|
pde = ldl_phys(pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
/* if PSE bit is set, then we use a 4MB page */
|
|
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
|
page_size = 4096 * 1024;
|
|
if (is_user) {
|
|
if (!(pde & PG_USER_MASK))
|
|
goto do_fault_protect;
|
|
if (is_write && !(pde & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
} else {
|
|
if ((env->cr[0] & CR0_WP_MASK) &&
|
|
is_write && !(pde & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
}
|
|
is_dirty = is_write && !(pde & PG_DIRTY_MASK);
|
|
if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
if (is_dirty)
|
|
pde |= PG_DIRTY_MASK;
|
|
stl_phys_notdirty(pde_addr, pde);
|
|
}
|
|
|
|
pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
|
|
ptep = pte;
|
|
virt_addr = addr & ~(page_size - 1);
|
|
} else {
|
|
if (!(pde & PG_ACCESSED_MASK)) {
|
|
pde |= PG_ACCESSED_MASK;
|
|
stl_phys_notdirty(pde_addr, pde);
|
|
}
|
|
|
|
/* page directory entry */
|
|
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
|
|
env->a20_mask;
|
|
pte = ldl_phys(pte_addr);
|
|
if (!(pte & PG_PRESENT_MASK)) {
|
|
error_code = 0;
|
|
goto do_fault;
|
|
}
|
|
/* combine pde and pte user and rw protections */
|
|
ptep = pte & pde;
|
|
if (is_user) {
|
|
if (!(ptep & PG_USER_MASK))
|
|
goto do_fault_protect;
|
|
if (is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
} else {
|
|
if ((env->cr[0] & CR0_WP_MASK) &&
|
|
is_write && !(ptep & PG_RW_MASK))
|
|
goto do_fault_protect;
|
|
}
|
|
is_dirty = is_write && !(pte & PG_DIRTY_MASK);
|
|
if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
|
|
pte |= PG_ACCESSED_MASK;
|
|
if (is_dirty)
|
|
pte |= PG_DIRTY_MASK;
|
|
stl_phys_notdirty(pte_addr, pte);
|
|
}
|
|
page_size = 4096;
|
|
virt_addr = addr & ~0xfff;
|
|
}
|
|
}
|
|
/* the page can be put in the TLB */
|
|
prot = PAGE_READ;
|
|
if (!(ptep & PG_NX_MASK))
|
|
prot |= PAGE_EXEC;
|
|
if (pte & PG_DIRTY_MASK) {
|
|
/* only set write access if already dirty... otherwise wait
|
|
for dirty access */
|
|
if (is_user) {
|
|
if (ptep & PG_RW_MASK)
|
|
prot |= PAGE_WRITE;
|
|
} else {
|
|
if (!(env->cr[0] & CR0_WP_MASK) ||
|
|
(ptep & PG_RW_MASK))
|
|
prot |= PAGE_WRITE;
|
|
}
|
|
}
|
|
do_mapping:
|
|
pte = pte & env->a20_mask;
|
|
|
|
/* Even if 4MB pages, we map only one 4KB page in the cache to
|
|
avoid filling it too fast */
|
|
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
|
paddr = (pte & TARGET_PAGE_MASK) + page_offset;
|
|
vaddr = virt_addr + page_offset;
|
|
|
|
tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
|
|
return 0;
|
|
do_fault_protect:
|
|
error_code = PG_ERROR_P_MASK;
|
|
do_fault:
|
|
error_code |= (is_write << PG_ERROR_W_BIT);
|
|
if (is_user)
|
|
error_code |= PG_ERROR_U_MASK;
|
|
if (is_write1 == 2 &&
|
|
(env->efer & MSR_EFER_NXE) &&
|
|
(env->cr[4] & CR4_PAE_MASK))
|
|
error_code |= PG_ERROR_I_D_MASK;
|
|
if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
|
|
/* cr2 is not modified in case of exceptions */
|
|
stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
|
|
addr);
|
|
} else {
|
|
env->cr[2] = addr;
|
|
}
|
|
env->error_code = error_code;
|
|
env->exception_index = EXCP0E_PAGE;
|
|
return 1;
|
|
}
|
|
|
|
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
|
|
{
|
|
target_ulong pde_addr, pte_addr;
|
|
uint64_t pte;
|
|
target_phys_addr_t paddr;
|
|
uint32_t page_offset;
|
|
int page_size;
|
|
|
|
if (env->cr[4] & CR4_PAE_MASK) {
|
|
target_ulong pdpe_addr;
|
|
uint64_t pde, pdpe;
|
|
|
|
#ifdef TARGET_X86_64
|
|
if (env->hflags & HF_LMA_MASK) {
|
|
uint64_t pml4e_addr, pml4e;
|
|
int32_t sext;
|
|
|
|
/* test virtual address sign extension */
|
|
sext = (int64_t)addr >> 47;
|
|
if (sext != 0 && sext != -1)
|
|
return -1;
|
|
|
|
pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
|
|
env->a20_mask;
|
|
pml4e = ldq_phys(pml4e_addr);
|
|
if (!(pml4e & PG_PRESENT_MASK))
|
|
return -1;
|
|
|
|
pdpe_addr = ((pml4e & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
|
|
(((addr >> 30) & 0x1ff) << 3)) & env->a20_mask;
|
|
pdpe = ldq_phys(pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK))
|
|
return -1;
|
|
} else
|
|
#endif
|
|
{
|
|
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
|
|
env->a20_mask;
|
|
pdpe = ldq_phys(pdpe_addr);
|
|
if (!(pdpe & PG_PRESENT_MASK))
|
|
return -1;
|
|
}
|
|
|
|
pde_addr = ((pdpe & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
|
|
(((addr >> 21) & 0x1ff) << 3)) & env->a20_mask;
|
|
pde = ldq_phys(pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK)) {
|
|
return -1;
|
|
}
|
|
if (pde & PG_PSE_MASK) {
|
|
/* 2 MB page */
|
|
page_size = 2048 * 1024;
|
|
pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
|
|
} else {
|
|
/* 4 KB page */
|
|
pte_addr = ((pde & ~0xfff & ~(PG_NX_MASK | PG_HI_USER_MASK)) +
|
|
(((addr >> 12) & 0x1ff) << 3)) & env->a20_mask;
|
|
page_size = 4096;
|
|
pte = ldq_phys(pte_addr);
|
|
}
|
|
pte &= ~(PG_NX_MASK | PG_HI_USER_MASK);
|
|
if (!(pte & PG_PRESENT_MASK))
|
|
return -1;
|
|
} else {
|
|
uint32_t pde;
|
|
|
|
if (!(env->cr[0] & CR0_PG_MASK)) {
|
|
pte = addr;
|
|
page_size = 4096;
|
|
} else {
|
|
/* page directory entry */
|
|
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
|
|
pde = ldl_phys(pde_addr);
|
|
if (!(pde & PG_PRESENT_MASK))
|
|
return -1;
|
|
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
|
pte = pde & ~0x003ff000; /* align to 4MB */
|
|
page_size = 4096 * 1024;
|
|
} else {
|
|
/* page directory entry */
|
|
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
|
|
pte = ldl_phys(pte_addr);
|
|
if (!(pte & PG_PRESENT_MASK))
|
|
return -1;
|
|
page_size = 4096;
|
|
}
|
|
}
|
|
pte = pte & env->a20_mask;
|
|
}
|
|
|
|
page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
|
|
paddr = (pte & TARGET_PAGE_MASK) + page_offset;
|
|
return paddr;
|
|
}
|
|
|
|
void hw_breakpoint_insert(CPUState *env, int index)
|
|
{
|
|
int type, err = 0;
|
|
|
|
switch (hw_breakpoint_type(env->dr[7], index)) {
|
|
case 0:
|
|
if (hw_breakpoint_enabled(env->dr[7], index))
|
|
err = cpu_breakpoint_insert(env, env->dr[index], BP_CPU,
|
|
&env->cpu_breakpoint[index]);
|
|
break;
|
|
case 1:
|
|
type = BP_CPU | BP_MEM_WRITE;
|
|
goto insert_wp;
|
|
case 2:
|
|
/* No support for I/O watchpoints yet */
|
|
break;
|
|
case 3:
|
|
type = BP_CPU | BP_MEM_ACCESS;
|
|
insert_wp:
|
|
err = cpu_watchpoint_insert(env, env->dr[index],
|
|
hw_breakpoint_len(env->dr[7], index),
|
|
type, &env->cpu_watchpoint[index]);
|
|
break;
|
|
}
|
|
if (err)
|
|
env->cpu_breakpoint[index] = NULL;
|
|
}
|
|
|
|
void hw_breakpoint_remove(CPUState *env, int index)
|
|
{
|
|
if (!env->cpu_breakpoint[index])
|
|
return;
|
|
switch (hw_breakpoint_type(env->dr[7], index)) {
|
|
case 0:
|
|
if (hw_breakpoint_enabled(env->dr[7], index))
|
|
cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[index]);
|
|
break;
|
|
case 1:
|
|
case 3:
|
|
cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[index]);
|
|
break;
|
|
case 2:
|
|
/* No support for I/O watchpoints yet */
|
|
break;
|
|
}
|
|
}
|
|
|
|
int check_hw_breakpoints(CPUState *env, int force_dr6_update)
|
|
{
|
|
target_ulong dr6;
|
|
int reg, type;
|
|
int hit_enabled = 0;
|
|
|
|
dr6 = env->dr[6] & ~0xf;
|
|
for (reg = 0; reg < 4; reg++) {
|
|
type = hw_breakpoint_type(env->dr[7], reg);
|
|
if ((type == 0 && env->dr[reg] == env->eip) ||
|
|
((type & 1) && env->cpu_watchpoint[reg] &&
|
|
(env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT))) {
|
|
dr6 |= 1 << reg;
|
|
if (hw_breakpoint_enabled(env->dr[7], reg))
|
|
hit_enabled = 1;
|
|
}
|
|
}
|
|
if (hit_enabled || force_dr6_update)
|
|
env->dr[6] = dr6;
|
|
return hit_enabled;
|
|
}
|
|
|
|
static CPUDebugExcpHandler *prev_debug_excp_handler;
|
|
|
|
static void breakpoint_handler(CPUState *env)
|
|
{
|
|
CPUBreakpoint *bp;
|
|
|
|
if (env->watchpoint_hit) {
|
|
if (env->watchpoint_hit->flags & BP_CPU) {
|
|
env->watchpoint_hit = NULL;
|
|
if (check_hw_breakpoints(env, 0))
|
|
raise_exception_env(EXCP01_DB, env);
|
|
else
|
|
cpu_resume_from_signal(env, NULL);
|
|
}
|
|
} else {
|
|
QTAILQ_FOREACH(bp, &env->breakpoints, entry)
|
|
if (bp->pc == env->eip) {
|
|
if (bp->flags & BP_CPU) {
|
|
check_hw_breakpoints(env, 1);
|
|
raise_exception_env(EXCP01_DB, env);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
if (prev_debug_excp_handler)
|
|
prev_debug_excp_handler(env);
|
|
}
|
|
|
|
typedef struct MCEInjectionParams {
|
|
Monitor *mon;
|
|
CPUState *env;
|
|
int bank;
|
|
uint64_t status;
|
|
uint64_t mcg_status;
|
|
uint64_t addr;
|
|
uint64_t misc;
|
|
int flags;
|
|
} MCEInjectionParams;
|
|
|
|
static void do_inject_x86_mce(void *data)
|
|
{
|
|
MCEInjectionParams *params = data;
|
|
CPUState *cenv = params->env;
|
|
uint64_t *banks = cenv->mce_banks + 4 * params->bank;
|
|
|
|
cpu_synchronize_state(cenv);
|
|
|
|
/*
|
|
* If there is an MCE exception being processed, ignore this SRAO MCE
|
|
* unless unconditional injection was requested.
|
|
*/
|
|
if (!(params->flags & MCE_INJECT_UNCOND_AO)
|
|
&& !(params->status & MCI_STATUS_AR)
|
|
&& (cenv->mcg_status & MCG_STATUS_MCIP)) {
|
|
return;
|
|
}
|
|
|
|
if (params->status & MCI_STATUS_UC) {
|
|
/*
|
|
* if MSR_MCG_CTL is not all 1s, the uncorrected error
|
|
* reporting is disabled
|
|
*/
|
|
if ((cenv->mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) {
|
|
monitor_printf(params->mon,
|
|
"CPU %d: Uncorrected error reporting disabled\n",
|
|
cenv->cpu_index);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* if MSR_MCi_CTL is not all 1s, the uncorrected error
|
|
* reporting is disabled for the bank
|
|
*/
|
|
if (banks[0] != ~(uint64_t)0) {
|
|
monitor_printf(params->mon,
|
|
"CPU %d: Uncorrected error reporting disabled for"
|
|
" bank %d\n",
|
|
cenv->cpu_index, params->bank);
|
|
return;
|
|
}
|
|
|
|
if ((cenv->mcg_status & MCG_STATUS_MCIP) ||
|
|
!(cenv->cr[4] & CR4_MCE_MASK)) {
|
|
monitor_printf(params->mon,
|
|
"CPU %d: Previous MCE still in progress, raising"
|
|
" triple fault\n",
|
|
cenv->cpu_index);
|
|
qemu_log_mask(CPU_LOG_RESET, "Triple fault\n");
|
|
qemu_system_reset_request();
|
|
return;
|
|
}
|
|
if (banks[1] & MCI_STATUS_VAL) {
|
|
params->status |= MCI_STATUS_OVER;
|
|
}
|
|
banks[2] = params->addr;
|
|
banks[3] = params->misc;
|
|
cenv->mcg_status = params->mcg_status;
|
|
banks[1] = params->status;
|
|
cpu_interrupt(cenv, CPU_INTERRUPT_MCE);
|
|
} else if (!(banks[1] & MCI_STATUS_VAL)
|
|
|| !(banks[1] & MCI_STATUS_UC)) {
|
|
if (banks[1] & MCI_STATUS_VAL) {
|
|
params->status |= MCI_STATUS_OVER;
|
|
}
|
|
banks[2] = params->addr;
|
|
banks[3] = params->misc;
|
|
banks[1] = params->status;
|
|
} else {
|
|
banks[1] |= MCI_STATUS_OVER;
|
|
}
|
|
}
|
|
|
|
void cpu_x86_inject_mce(Monitor *mon, CPUState *cenv, int bank,
|
|
uint64_t status, uint64_t mcg_status, uint64_t addr,
|
|
uint64_t misc, int flags)
|
|
{
|
|
MCEInjectionParams params = {
|
|
.mon = mon,
|
|
.env = cenv,
|
|
.bank = bank,
|
|
.status = status,
|
|
.mcg_status = mcg_status,
|
|
.addr = addr,
|
|
.misc = misc,
|
|
.flags = flags,
|
|
};
|
|
unsigned bank_num = cenv->mcg_cap & 0xff;
|
|
CPUState *env;
|
|
|
|
if (!cenv->mcg_cap) {
|
|
monitor_printf(mon, "MCE injection not supported\n");
|
|
return;
|
|
}
|
|
if (bank >= bank_num) {
|
|
monitor_printf(mon, "Invalid MCE bank number\n");
|
|
return;
|
|
}
|
|
if (!(status & MCI_STATUS_VAL)) {
|
|
monitor_printf(mon, "Invalid MCE status code\n");
|
|
return;
|
|
}
|
|
if ((flags & MCE_INJECT_BROADCAST)
|
|
&& !cpu_x86_support_mca_broadcast(cenv)) {
|
|
monitor_printf(mon, "Guest CPU does not support MCA broadcast\n");
|
|
return;
|
|
}
|
|
|
|
run_on_cpu(cenv, do_inject_x86_mce, ¶ms);
|
|
if (flags & MCE_INJECT_BROADCAST) {
|
|
params.bank = 1;
|
|
params.status = MCI_STATUS_VAL | MCI_STATUS_UC;
|
|
params.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
|
|
params.addr = 0;
|
|
params.misc = 0;
|
|
for (env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
if (cenv == env) {
|
|
continue;
|
|
}
|
|
params.env = env;
|
|
run_on_cpu(cenv, do_inject_x86_mce, ¶ms);
|
|
}
|
|
}
|
|
}
|
|
|
|
void cpu_report_tpr_access(CPUState *env, TPRAccess access)
|
|
{
|
|
TranslationBlock *tb;
|
|
|
|
if (kvm_enabled()) {
|
|
env->tpr_access_type = access;
|
|
|
|
cpu_interrupt(env, CPU_INTERRUPT_TPR);
|
|
} else {
|
|
tb = tb_find_pc(env->mem_io_pc);
|
|
cpu_restore_state(tb, env, env->mem_io_pc);
|
|
|
|
apic_handle_tpr_access_report(env->apic_state, env->eip, access);
|
|
}
|
|
}
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
static void mce_init(CPUX86State *cenv)
|
|
{
|
|
unsigned int bank;
|
|
|
|
if (((cenv->cpuid_version >> 8) & 0xf) >= 6
|
|
&& (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
|
|
(CPUID_MCE | CPUID_MCA)) {
|
|
cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
|
|
cenv->mcg_ctl = ~(uint64_t)0;
|
|
for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
|
|
cenv->mce_banks[bank * 4] = ~(uint64_t)0;
|
|
}
|
|
}
|
|
}
|
|
|
|
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
|
|
target_ulong *base, unsigned int *limit,
|
|
unsigned int *flags)
|
|
{
|
|
SegmentCache *dt;
|
|
target_ulong ptr;
|
|
uint32_t e1, e2;
|
|
int index;
|
|
|
|
if (selector & 0x4)
|
|
dt = &env->ldt;
|
|
else
|
|
dt = &env->gdt;
|
|
index = selector & ~7;
|
|
ptr = dt->base + index;
|
|
if ((index + 7) > dt->limit
|
|
|| cpu_memory_rw_debug(env, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
|
|
|| cpu_memory_rw_debug(env, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
|
|
return 0;
|
|
|
|
*base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
|
|
*limit = (e1 & 0xffff) | (e2 & 0x000f0000);
|
|
if (e2 & DESC_G_MASK)
|
|
*limit = (*limit << 12) | 0xfff;
|
|
*flags = e2;
|
|
|
|
return 1;
|
|
}
|
|
|
|
CPUX86State *cpu_x86_init(const char *cpu_model)
|
|
{
|
|
CPUX86State *env;
|
|
static int inited;
|
|
|
|
env = g_malloc0(sizeof(CPUX86State));
|
|
cpu_exec_init(env);
|
|
env->cpu_model_str = cpu_model;
|
|
|
|
/* init various static tables used in TCG mode */
|
|
if (tcg_enabled() && !inited) {
|
|
inited = 1;
|
|
optimize_flags_init();
|
|
#ifndef CONFIG_USER_ONLY
|
|
prev_debug_excp_handler =
|
|
cpu_set_debug_excp_handler(breakpoint_handler);
|
|
#endif
|
|
}
|
|
if (cpu_x86_register(env, cpu_model) < 0) {
|
|
cpu_x86_close(env);
|
|
return NULL;
|
|
}
|
|
env->cpuid_apic_id = env->cpu_index;
|
|
mce_init(env);
|
|
|
|
qemu_init_vcpu(env);
|
|
|
|
return env;
|
|
}
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
void do_cpu_init(CPUState *env)
|
|
{
|
|
int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI;
|
|
uint64_t pat = env->pat;
|
|
|
|
cpu_state_reset(env);
|
|
env->interrupt_request = sipi;
|
|
env->pat = pat;
|
|
apic_init_reset(env->apic_state);
|
|
env->halted = !cpu_is_bsp(env);
|
|
}
|
|
|
|
void do_cpu_sipi(CPUState *env)
|
|
{
|
|
apic_sipi(env->apic_state);
|
|
}
|
|
#else
|
|
void do_cpu_init(CPUState *env)
|
|
{
|
|
}
|
|
void do_cpu_sipi(CPUState *env)
|
|
{
|
|
}
|
|
#endif
|