148 lines
4.5 KiB
C
148 lines
4.5 KiB
C
/*
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* QEMU MIPS timer support
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h"
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#include "hw/mips_cpudevs.h"
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#include "qemu/timer.h"
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#define TIMER_FREQ 100 * 1000 * 1000
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/* XXX: do not use a global */
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uint32_t cpu_mips_get_random (CPUMIPSState *env)
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{
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static uint32_t lfsr = 1;
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static uint32_t prev_idx = 0;
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uint32_t idx;
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/* Don't return same value twice, so get another value */
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do {
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lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
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idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
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} while (idx == prev_idx);
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prev_idx = idx;
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return idx;
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}
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/* MIPS R4K timer */
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static void cpu_mips_timer_update(CPUMIPSState *env)
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{
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uint64_t now, next;
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uint32_t wait;
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now = qemu_get_clock_ns(vm_clock);
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wait = env->CP0_Compare - env->CP0_Count -
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(uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
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next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
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qemu_mod_timer(env->timer, next);
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}
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/* Expire the timer. */
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static void cpu_mips_timer_expire(CPUMIPSState *env)
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{
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cpu_mips_timer_update(env);
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if (env->insn_flags & ISA_MIPS32R2) {
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env->CP0_Cause |= 1 << CP0Ca_TI;
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}
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qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
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}
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uint32_t cpu_mips_get_count (CPUMIPSState *env)
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{
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if (env->CP0_Cause & (1 << CP0Ca_DC)) {
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return env->CP0_Count;
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} else {
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uint64_t now;
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now = qemu_get_clock_ns(vm_clock);
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if (qemu_timer_pending(env->timer)
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&& qemu_timer_expired(env->timer, now)) {
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/* The timer has already expired. */
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cpu_mips_timer_expire(env);
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}
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return env->CP0_Count +
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(uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
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}
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}
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void cpu_mips_store_count (CPUMIPSState *env, uint32_t count)
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{
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if (env->CP0_Cause & (1 << CP0Ca_DC))
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env->CP0_Count = count;
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else {
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/* Store new count register */
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env->CP0_Count =
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count - (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
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TIMER_FREQ, get_ticks_per_sec());
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/* Update timer timer */
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cpu_mips_timer_update(env);
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}
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}
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void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value)
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{
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env->CP0_Compare = value;
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if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
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cpu_mips_timer_update(env);
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if (env->insn_flags & ISA_MIPS32R2)
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env->CP0_Cause &= ~(1 << CP0Ca_TI);
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qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
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}
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void cpu_mips_start_count(CPUMIPSState *env)
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{
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cpu_mips_store_count(env, env->CP0_Count);
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}
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void cpu_mips_stop_count(CPUMIPSState *env)
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{
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/* Store the current value */
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env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock_ns(vm_clock),
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TIMER_FREQ, get_ticks_per_sec());
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}
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static void mips_timer_cb (void *opaque)
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{
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CPUMIPSState *env;
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env = opaque;
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#if 0
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qemu_log("%s\n", __func__);
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#endif
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if (env->CP0_Cause & (1 << CP0Ca_DC))
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return;
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/* ??? This callback should occur when the counter is exactly equal to
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the comparator value. Offset the count by one to avoid immediately
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retriggering the callback before any virtual time has passed. */
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env->CP0_Count++;
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cpu_mips_timer_expire(env);
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env->CP0_Count--;
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}
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void cpu_mips_clock_init (CPUMIPSState *env)
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{
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env->timer = qemu_new_timer_ns(vm_clock, &mips_timer_cb, env);
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env->CP0_Compare = 0;
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cpu_mips_store_count(env, 1);
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}
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