1101 lines
62 KiB
C
1101 lines
62 KiB
C
/* Disassemble Xilinx microblaze instructions.
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Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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/*
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* Copyright (c) 2001 Xilinx, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms are permitted
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* provided that the above copyright notice and this paragraph are
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* duplicated in all such forms and that any documentation,
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* advertising materials, and other materials related to such
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* distribution and use acknowledge that the software was developed
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* by Xilinx, Inc. The name of the Company may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Xilinx, Inc.
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*/
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#include <stdio.h>
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#define STATIC_TABLE
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#define DEFINE_TABLE
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#define TRUE 1
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#define FALSE 0
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#ifndef MICROBLAZE_OPC
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#define MICROBLAZE_OPC
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/* Assembler instructions for Xilinx's microblaze processor
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Copyright (C) 1999, 2000 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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/*
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* Copyright (c) 2001 Xilinx, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms are permitted
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* provided that the above copyright notice and this paragraph are
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* duplicated in all such forms and that any documentation,
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* advertising materials, and other materials related to such
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* distribution and use acknowledge that the software was developed
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* by Xilinx, Inc. The name of the Company may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Xilinx, Inc.
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*/
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#ifndef MICROBLAZE_OPCM
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#define MICROBLAZE_OPCM
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/*
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* Copyright (c) 2001 Xilinx, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms are permitted
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* provided that the above copyright notice and this paragraph are
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* duplicated in all such forms and that any documentation,
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* advertising materials, and other materials related to such
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* distribution and use acknowledge that the software was developed
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* by Xilinx, Inc. The name of the Company may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Xilinx, Inc.
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* $Header:
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*/
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enum microblaze_instr {
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add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu,
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addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, mulh, mulhu, mulhsu,
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idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
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ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
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andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, wic, wdc, wdcclear, wdcflush, mts, mfs, br, brd,
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brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
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bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
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imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
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brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
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bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
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sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
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fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, fint, fsqrt,
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tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
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eget, ecget, neget, necget, eput, ecput, neput, necput,
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teget, tecget, tneget, tnecget, teput, tecput, tneput, tnecput,
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aget, caget, naget, ncaget, aput, caput, naput, ncaput,
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taget, tcaget, tnaget, tncaget, taput, tcaput, tnaput, tncaput,
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eaget, ecaget, neaget, necaget, eaput, ecaput, neaput, necaput,
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teaget, tecaget, tneaget, tnecaget, teaput, tecaput, tneaput, tnecaput,
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getd, tgetd, cgetd, tcgetd, ngetd, tngetd, ncgetd, tncgetd,
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putd, tputd, cputd, tcputd, nputd, tnputd, ncputd, tncputd,
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egetd, tegetd, ecgetd, tecgetd, negetd, tnegetd, necgetd, tnecgetd,
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eputd, teputd, ecputd, tecputd, neputd, tneputd, necputd, tnecputd,
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agetd, tagetd, cagetd, tcagetd, nagetd, tnagetd, ncagetd, tncagetd,
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aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
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eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
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eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
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invalid_inst } ;
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enum microblaze_instr_type {
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arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst,
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return_inst, immediate_inst, special_inst, memory_load_inst,
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memory_store_inst, barrel_shift_inst, anyware_inst };
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#define INST_WORD_SIZE 4
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/* gen purpose regs go from 0 to 31 */
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/* mask is reg num - max_reg_num, ie reg_num - 32 in this case */
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#define REG_PC_MASK 0x8000
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#define REG_MSR_MASK 0x8001
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#define REG_EAR_MASK 0x8003
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#define REG_ESR_MASK 0x8005
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#define REG_FSR_MASK 0x8007
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#define REG_BTR_MASK 0x800b
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#define REG_EDR_MASK 0x800d
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#define REG_PVR_MASK 0xa000
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#define REG_PID_MASK 0x9000
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#define REG_ZPR_MASK 0x9001
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#define REG_TLBX_MASK 0x9002
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#define REG_TLBLO_MASK 0x9003
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#define REG_TLBHI_MASK 0x9004
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#define REG_TLBSX_MASK 0x9005
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#define MIN_REGNUM 0
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#define MAX_REGNUM 31
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#define MIN_PVR_REGNUM 0
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#define MAX_PVR_REGNUM 15
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#define REG_PC 32 /* PC */
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#define REG_MSR 33 /* machine status reg */
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#define REG_EAR 35 /* Exception reg */
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#define REG_ESR 37 /* Exception reg */
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#define REG_FSR 39 /* FPU Status reg */
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#define REG_BTR 43 /* Branch Target reg */
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#define REG_EDR 45 /* Exception reg */
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#define REG_PVR 40960 /* Program Verification reg */
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#define REG_PID 36864 /* MMU: Process ID reg */
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#define REG_ZPR 36865 /* MMU: Zone Protect reg */
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#define REG_TLBX 36866 /* MMU: TLB Index reg */
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#define REG_TLBLO 36867 /* MMU: TLB Low reg */
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#define REG_TLBHI 36868 /* MMU: TLB High reg */
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#define REG_TLBSX 36869 /* MMU: TLB Search Index reg */
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/* alternate names for gen purpose regs */
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#define REG_SP 1 /* stack pointer */
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#define REG_ROSDP 2 /* read-only small data pointer */
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#define REG_RWSDP 13 /* read-write small data pointer */
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/* Assembler Register - Used in Delay Slot Optimization */
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#define REG_AS 18
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#define REG_ZERO 0
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#define RD_LOW 21 /* low bit for RD */
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#define RA_LOW 16 /* low bit for RA */
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#define RB_LOW 11 /* low bit for RB */
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#define IMM_LOW 0 /* low bit for immediate */
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#define RD_MASK 0x03E00000
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#define RA_MASK 0x001F0000
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#define RB_MASK 0x0000F800
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#define IMM_MASK 0x0000FFFF
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// imm mask for barrel shifts
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#define IMM5_MASK 0x0000001F
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// FSL imm mask for get, put instructions
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#define RFSL_MASK 0x000000F
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// imm mask for msrset, msrclr instructions
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#define IMM15_MASK 0x00007FFF
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#endif /* MICROBLAZE-OPCM */
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#define INST_TYPE_RD_R1_R2 0
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#define INST_TYPE_RD_R1_IMM 1
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#define INST_TYPE_RD_R1_UNSIGNED_IMM 2
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#define INST_TYPE_RD_R1 3
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#define INST_TYPE_RD_R2 4
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#define INST_TYPE_RD_IMM 5
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#define INST_TYPE_R2 6
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#define INST_TYPE_R1_R2 7
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#define INST_TYPE_R1_IMM 8
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#define INST_TYPE_IMM 9
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#define INST_TYPE_SPECIAL_R1 10
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#define INST_TYPE_RD_SPECIAL 11
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#define INST_TYPE_R1 12
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// new instn type for barrel shift imms
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#define INST_TYPE_RD_R1_IMM5 13
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#define INST_TYPE_RD_RFSL 14
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#define INST_TYPE_R1_RFSL 15
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// new insn type for insn cache
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#define INST_TYPE_RD_R1_SPECIAL 16
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// new insn type for msrclr, msrset insns.
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#define INST_TYPE_RD_IMM15 17
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// new insn type for tuqula rd - addik rd, r0, 42
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#define INST_TYPE_RD 18
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// new insn type for t*put
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#define INST_TYPE_RFSL 19
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#define INST_TYPE_NONE 25
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#define INST_PC_OFFSET 1 /* instructions where the label address is resolved as a PC offset (for branch label)*/
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#define INST_NO_OFFSET 0 /* instructions where the label address is resolved as an absolute value (for data mem or abs address)*/
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#define IMMVAL_MASK_NON_SPECIAL 0x0000
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#define IMMVAL_MASK_MTS 0x4000
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#define IMMVAL_MASK_MFS 0x0000
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#define OPCODE_MASK_H 0xFC000000 /* High 6 bits only */
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#define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits */
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#define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16 */
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#define OPCODE_MASK_H12 0xFFFF0000 /* High 16 */
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#define OPCODE_MASK_H4 0xFC0007FF /* High 6 and low 11 bits */
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#define OPCODE_MASK_H13S 0xFFE0EFF0 /* High 11 and 15:1 bits and last nibble of last byte for spr */
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#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last nibble of last byte for spr */
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#define OPCODE_MASK_H34 0xFC00FFFF /* High 6 and low 16 bits */
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#define OPCODE_MASK_H14 0xFFE007FF /* High 11 and low 11 bits */
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#define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits */
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#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits */
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#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits */
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#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22 */
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#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21 */
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#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits */
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#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26 */
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// New Mask for msrset, msrclr insns.
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#define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16 */
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#define DELAY_SLOT 1
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#define NO_DELAY_SLOT 0
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#define MAX_OPCODES 280
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struct op_code_struct {
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const char *name;
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short inst_type; /* registers and immediate values involved */
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short inst_offset_type; /* immediate vals offset from PC? (= 1 for branches) */
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short delay_slots; /* info about delay slots needed after this instr. */
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short immval_mask;
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unsigned long bit_sequence; /* all the fixed bits for the op are set and all the variable bits (reg names, imm vals) are set to 0 */
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unsigned long opcode_mask; /* which bits define the opcode */
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enum microblaze_instr instr;
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enum microblaze_instr_type instr_type;
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/* more info about output format here */
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} opcodes[MAX_OPCODES] =
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{
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{"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
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{"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
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{"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
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{"rsubc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000000, OPCODE_MASK_H4, rsubc, arithmetic_inst },
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{"addk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000000, OPCODE_MASK_H4, addk, arithmetic_inst },
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{"rsubk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000000, OPCODE_MASK_H4, rsubk, arithmetic_inst },
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{"cmp", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000001, OPCODE_MASK_H4, cmp, arithmetic_inst },
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{"cmpu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000003, OPCODE_MASK_H4, cmpu, arithmetic_inst },
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{"addkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000000, OPCODE_MASK_H4, addkc, arithmetic_inst },
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{"rsubkc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000000, OPCODE_MASK_H4, rsubkc, arithmetic_inst },
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{"addi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, addi, arithmetic_inst },
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{"rsubi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, rsubi, arithmetic_inst },
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{"addic", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, addic, arithmetic_inst },
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{"rsubic",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, rsubic, arithmetic_inst },
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{"addik", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, addik, arithmetic_inst },
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{"rsubik",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, rsubik, arithmetic_inst },
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{"addikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, addikc, arithmetic_inst },
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{"rsubikc",INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, rsubikc, arithmetic_inst },
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{"mul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000000, OPCODE_MASK_H4, mul, mult_inst },
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{"mulh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000001, OPCODE_MASK_H4, mulh, mult_inst },
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{"mulhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000003, OPCODE_MASK_H4, mulhu, mult_inst },
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{"mulhsu",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000002, OPCODE_MASK_H4, mulhsu, mult_inst },
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{"idiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst },
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{"idivu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000002, OPCODE_MASK_H4, idivu, div_inst },
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{"bsll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000400, OPCODE_MASK_H3, bsll, barrel_shift_inst },
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{"bsra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000200, OPCODE_MASK_H3, bsra, barrel_shift_inst },
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{"bsrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000000, OPCODE_MASK_H3, bsrl, barrel_shift_inst },
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{"get", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000000, OPCODE_MASK_H32, get, anyware_inst },
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{"put", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008000, OPCODE_MASK_H32, put, anyware_inst },
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{"nget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004000, OPCODE_MASK_H32, nget, anyware_inst },
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{"nput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C000, OPCODE_MASK_H32, nput, anyware_inst },
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{"cget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002000, OPCODE_MASK_H32, cget, anyware_inst },
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{"cput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A000, OPCODE_MASK_H32, cput, anyware_inst },
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{"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
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{"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
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{"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
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{"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
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{"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
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{"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
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{"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, or, logical_inst },
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{"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, and, logical_inst },
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{"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, xor, logical_inst },
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{"andn", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000000, OPCODE_MASK_H4, andn, logical_inst },
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{"pcmpbf",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000400, OPCODE_MASK_H4, pcmpbf, logical_inst },
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{"pcmpbc",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000400, OPCODE_MASK_H4, pcmpbc, logical_inst },
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{"pcmpeq",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000400, OPCODE_MASK_H4, pcmpeq, logical_inst },
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{"pcmpne",INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000400, OPCODE_MASK_H4, pcmpne, logical_inst },
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{"sra", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000001, OPCODE_MASK_H34, sra, logical_inst },
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{"src", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000021, OPCODE_MASK_H34, src, logical_inst },
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{"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
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{"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst },
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{"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
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{"wic", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
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{"wdc", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
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{"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
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{"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
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{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
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{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
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{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
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{"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
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{"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
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{"bra", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98080000, OPCODE_MASK_H124, bra, branch_inst },
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{"brad", INST_TYPE_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98180000, OPCODE_MASK_H124, brad, branch_inst },
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{"brald", INST_TYPE_RD_R2, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x981C0000, OPCODE_MASK_H24, brald, branch_inst },
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{"brk", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x980C0000, OPCODE_MASK_H24, microblaze_brk, branch_inst },
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{"beq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C000000, OPCODE_MASK_H14, beq, branch_inst },
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{"beqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E000000, OPCODE_MASK_H14, beqd, branch_inst },
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{"bne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C200000, OPCODE_MASK_H14, bne, branch_inst },
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{"bned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E200000, OPCODE_MASK_H14, bned, branch_inst },
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{"blt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C400000, OPCODE_MASK_H14, blt, branch_inst },
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{"bltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E400000, OPCODE_MASK_H14, bltd, branch_inst },
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{"ble", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C600000, OPCODE_MASK_H14, ble, branch_inst },
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{"bled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E600000, OPCODE_MASK_H14, bled, branch_inst },
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{"bgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9C800000, OPCODE_MASK_H14, bgt, branch_inst },
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{"bgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9E800000, OPCODE_MASK_H14, bgtd, branch_inst },
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{"bge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9CA00000, OPCODE_MASK_H14, bge, branch_inst },
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{"bged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9EA00000, OPCODE_MASK_H14, bged, branch_inst },
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{"ori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, ori, logical_inst },
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{"andi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst },
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{"xori", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, xori, logical_inst },
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{"andni", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, andni, logical_inst },
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{"imm", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB0000000, OPCODE_MASK_H12, imm, immediate_inst },
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{"rtsd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000000, OPCODE_MASK_H1, rtsd, return_inst },
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{"rtid", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6200000, OPCODE_MASK_H1, rtid, return_inst },
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{"rtbd", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6400000, OPCODE_MASK_H1, rtbd, return_inst },
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{"rted", INST_TYPE_R1_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6800000, OPCODE_MASK_H1, rted, return_inst },
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{"bri", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8000000, OPCODE_MASK_H12, bri, branch_inst },
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{"brid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8100000, OPCODE_MASK_H12, brid, branch_inst },
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{"brlid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8140000, OPCODE_MASK_H2, brlid, branch_inst },
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{"brai", INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8080000, OPCODE_MASK_H12, brai, branch_inst },
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{"braid", INST_TYPE_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8180000, OPCODE_MASK_H12, braid, branch_inst },
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{"bralid",INST_TYPE_RD_IMM, INST_NO_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB81C0000, OPCODE_MASK_H2, bralid, branch_inst },
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{"brki", INST_TYPE_RD_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB80C0000, OPCODE_MASK_H2, brki, branch_inst },
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{"beqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC000000, OPCODE_MASK_H1, beqi, branch_inst },
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{"beqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE000000, OPCODE_MASK_H1, beqid, branch_inst },
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{"bnei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC200000, OPCODE_MASK_H1, bnei, branch_inst },
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{"bneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE200000, OPCODE_MASK_H1, bneid, branch_inst },
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{"blti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC400000, OPCODE_MASK_H1, blti, branch_inst },
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{"bltid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE400000, OPCODE_MASK_H1, bltid, branch_inst },
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{"blei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC600000, OPCODE_MASK_H1, blei, branch_inst },
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{"bleid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE600000, OPCODE_MASK_H1, bleid, branch_inst },
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{"bgti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBC800000, OPCODE_MASK_H1, bgti, branch_inst },
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{"bgtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBE800000, OPCODE_MASK_H1, bgtid, branch_inst },
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{"bgei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBCA00000, OPCODE_MASK_H1, bgei, branch_inst },
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{"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
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{"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
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{"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
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{"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
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{"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
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{"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
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{"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
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{"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
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{"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
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{"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
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{"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
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{"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
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{"sbi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF0000000, OPCODE_MASK_H, sbi, memory_store_inst },
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{"shi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF4000000, OPCODE_MASK_H, shi, memory_store_inst },
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{"swi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, swi, memory_store_inst },
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{"nop", INST_TYPE_NONE, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H1234, invalid_inst, logical_inst }, /* translates to or r0, r0, r0 */
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{"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik */
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{"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42 */
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{"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1 */
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{"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0 */
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{"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4 */
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{"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra */
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{"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
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{"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
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{"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
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{"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
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{"fadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
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{"frsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
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{"fmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
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{"fdiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
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{"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
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{"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
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{"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
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{"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst },
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{"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst },
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{"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
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{"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
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{"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst },
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{"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst },
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{"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst },
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{"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst },
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{"tcget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst },
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{"tnget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst },
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{"tncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007000, OPCODE_MASK_H32, tncget, anyware_inst },
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{"tput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009000, OPCODE_MASK_H32, tput, anyware_inst },
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{"tcput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B000, OPCODE_MASK_H32, tcput, anyware_inst },
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{"tnput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D000, OPCODE_MASK_H32, tnput, anyware_inst },
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{"tncput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F000, OPCODE_MASK_H32, tncput, anyware_inst },
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{"eget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000400, OPCODE_MASK_H32, eget, anyware_inst },
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{"ecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002400, OPCODE_MASK_H32, ecget, anyware_inst },
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{"neget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004400, OPCODE_MASK_H32, neget, anyware_inst },
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{"necget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006400, OPCODE_MASK_H32, necget, anyware_inst },
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{"eput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008400, OPCODE_MASK_H32, eput, anyware_inst },
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{"ecput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A400, OPCODE_MASK_H32, ecput, anyware_inst },
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{"neput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C400, OPCODE_MASK_H32, neput, anyware_inst },
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{"necput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E400, OPCODE_MASK_H32, necput, anyware_inst },
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{"teget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001400, OPCODE_MASK_H32, teget, anyware_inst },
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{"tecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003400, OPCODE_MASK_H32, tecget, anyware_inst },
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{"tneget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005400, OPCODE_MASK_H32, tneget, anyware_inst },
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{"tnecget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007400, OPCODE_MASK_H32, tnecget, anyware_inst },
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{"teput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009400, OPCODE_MASK_H32, teput, anyware_inst },
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{"tecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B400, OPCODE_MASK_H32, tecput, anyware_inst },
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{"tneput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D400, OPCODE_MASK_H32, tneput, anyware_inst },
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{"tnecput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F400, OPCODE_MASK_H32, tnecput, anyware_inst },
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{"aget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000800, OPCODE_MASK_H32, aget, anyware_inst },
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{"caget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002800, OPCODE_MASK_H32, caget, anyware_inst },
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{"naget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004800, OPCODE_MASK_H32, naget, anyware_inst },
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{"ncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006800, OPCODE_MASK_H32, ncaget, anyware_inst },
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{"aput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008800, OPCODE_MASK_H32, aput, anyware_inst },
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{"caput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00A800, OPCODE_MASK_H32, caput, anyware_inst },
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{"naput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00C800, OPCODE_MASK_H32, naput, anyware_inst },
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{"ncaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E800, OPCODE_MASK_H32, ncaput, anyware_inst },
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{"taget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001800, OPCODE_MASK_H32, taget, anyware_inst },
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{"tcaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003800, OPCODE_MASK_H32, tcaget, anyware_inst },
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{"tnaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005800, OPCODE_MASK_H32, tnaget, anyware_inst },
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{"tncaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007800, OPCODE_MASK_H32, tncaget, anyware_inst },
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{"taput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009800, OPCODE_MASK_H32, taput, anyware_inst },
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{"tcaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00B800, OPCODE_MASK_H32, tcaput, anyware_inst },
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{"tnaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00D800, OPCODE_MASK_H32, tnaput, anyware_inst },
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{"tncaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00F800, OPCODE_MASK_H32, tncaput, anyware_inst },
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{"eaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C000C00, OPCODE_MASK_H32, eget, anyware_inst },
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{"ecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C002C00, OPCODE_MASK_H32, ecget, anyware_inst },
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{"neaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C004C00, OPCODE_MASK_H32, neget, anyware_inst },
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{"necaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006C00, OPCODE_MASK_H32, necget, anyware_inst },
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{"eaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C008C00, OPCODE_MASK_H32, eput, anyware_inst },
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{"ecaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00AC00, OPCODE_MASK_H32, ecput, anyware_inst },
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{"neaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00CC00, OPCODE_MASK_H32, neput, anyware_inst },
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{"necaput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00EC00, OPCODE_MASK_H32, necput, anyware_inst },
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{"teaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001C00, OPCODE_MASK_H32, teaget, anyware_inst },
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{"tecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003C00, OPCODE_MASK_H32, tecaget, anyware_inst },
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{"tneaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005C00, OPCODE_MASK_H32, tneaget, anyware_inst },
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{"tnecaget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C007C00, OPCODE_MASK_H32, tnecaget, anyware_inst },
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{"teaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C009C00, OPCODE_MASK_H32, teaput, anyware_inst },
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{"tecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00BC00, OPCODE_MASK_H32, tecaput, anyware_inst },
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{"tneaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00DC00, OPCODE_MASK_H32, tneaput, anyware_inst },
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{"tnecaput", INST_TYPE_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00FC00, OPCODE_MASK_H32, tnecaput, anyware_inst },
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{"getd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000000, OPCODE_MASK_H34C, getd, anyware_inst },
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{"tgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000080, OPCODE_MASK_H34C, tgetd, anyware_inst },
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{"cgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000100, OPCODE_MASK_H34C, cgetd, anyware_inst },
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{"tcgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000180, OPCODE_MASK_H34C, tcgetd, anyware_inst },
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{"ngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000200, OPCODE_MASK_H34C, ngetd, anyware_inst },
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{"tngetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000280, OPCODE_MASK_H34C, tngetd, anyware_inst },
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{"ncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000300, OPCODE_MASK_H34C, ncgetd, anyware_inst },
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{"tncgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000380, OPCODE_MASK_H34C, tncgetd, anyware_inst },
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{"putd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000400, OPCODE_MASK_H34C, putd, anyware_inst },
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{"tputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000480, OPCODE_MASK_H34C, tputd, anyware_inst },
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{"cputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000500, OPCODE_MASK_H34C, cputd, anyware_inst },
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{"tcputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000580, OPCODE_MASK_H34C, tcputd, anyware_inst },
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{"nputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000600, OPCODE_MASK_H34C, nputd, anyware_inst },
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{"tnputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000680, OPCODE_MASK_H34C, tnputd, anyware_inst },
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{"ncputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000700, OPCODE_MASK_H34C, ncputd, anyware_inst },
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{"tncputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000780, OPCODE_MASK_H34C, tncputd, anyware_inst },
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{"egetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000020, OPCODE_MASK_H34C, egetd, anyware_inst },
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{"tegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000A0, OPCODE_MASK_H34C, tegetd, anyware_inst },
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{"ecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000120, OPCODE_MASK_H34C, ecgetd, anyware_inst },
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{"tecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001A0, OPCODE_MASK_H34C, tecgetd, anyware_inst },
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{"negetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000220, OPCODE_MASK_H34C, negetd, anyware_inst },
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{"tnegetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002A0, OPCODE_MASK_H34C, tnegetd, anyware_inst },
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{"necgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000320, OPCODE_MASK_H34C, necgetd, anyware_inst },
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{"tnecgetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003A0, OPCODE_MASK_H34C, tnecgetd, anyware_inst },
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{"eputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000420, OPCODE_MASK_H34C, eputd, anyware_inst },
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{"teputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004A0, OPCODE_MASK_H34C, teputd, anyware_inst },
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{"ecputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000520, OPCODE_MASK_H34C, ecputd, anyware_inst },
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{"tecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005A0, OPCODE_MASK_H34C, tecputd, anyware_inst },
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{"neputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000620, OPCODE_MASK_H34C, neputd, anyware_inst },
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{"tneputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006A0, OPCODE_MASK_H34C, tneputd, anyware_inst },
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{"necputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000720, OPCODE_MASK_H34C, necputd, anyware_inst },
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{"tnecputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007A0, OPCODE_MASK_H34C, tnecputd, anyware_inst },
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{"agetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000040, OPCODE_MASK_H34C, agetd, anyware_inst },
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{"tagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000C0, OPCODE_MASK_H34C, tagetd, anyware_inst },
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{"cagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000140, OPCODE_MASK_H34C, cagetd, anyware_inst },
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{"tcagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001C0, OPCODE_MASK_H34C, tcagetd, anyware_inst },
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{"nagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000240, OPCODE_MASK_H34C, nagetd, anyware_inst },
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{"tnagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002C0, OPCODE_MASK_H34C, tnagetd, anyware_inst },
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{"ncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000340, OPCODE_MASK_H34C, ncagetd, anyware_inst },
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{"tncagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003C0, OPCODE_MASK_H34C, tncagetd, anyware_inst },
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{"aputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000440, OPCODE_MASK_H34C, aputd, anyware_inst },
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{"taputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004C0, OPCODE_MASK_H34C, taputd, anyware_inst },
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{"caputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000540, OPCODE_MASK_H34C, caputd, anyware_inst },
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{"tcaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005C0, OPCODE_MASK_H34C, tcaputd, anyware_inst },
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{"naputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000640, OPCODE_MASK_H34C, naputd, anyware_inst },
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{"tnaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006C0, OPCODE_MASK_H34C, tnaputd, anyware_inst },
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{"ncaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000740, OPCODE_MASK_H34C, ncaputd, anyware_inst },
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{"tncaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007C0, OPCODE_MASK_H34C, tncaputd, anyware_inst },
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{"eagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000060, OPCODE_MASK_H34C, eagetd, anyware_inst },
|
|
{"teagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0000E0, OPCODE_MASK_H34C, teagetd, anyware_inst },
|
|
{"ecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000160, OPCODE_MASK_H34C, ecagetd, anyware_inst },
|
|
{"tecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0001E0, OPCODE_MASK_H34C, tecagetd, anyware_inst },
|
|
{"neagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000260, OPCODE_MASK_H34C, neagetd, anyware_inst },
|
|
{"tneagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0002E0, OPCODE_MASK_H34C, tneagetd, anyware_inst },
|
|
{"necagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000360, OPCODE_MASK_H34C, necagetd, anyware_inst },
|
|
{"tnecagetd", INST_TYPE_RD_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0003E0, OPCODE_MASK_H34C, tnecagetd, anyware_inst },
|
|
{"eaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000460, OPCODE_MASK_H34C, eaputd, anyware_inst },
|
|
{"teaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0004E0, OPCODE_MASK_H34C, teaputd, anyware_inst },
|
|
{"ecaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000560, OPCODE_MASK_H34C, ecaputd, anyware_inst },
|
|
{"tecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0005E0, OPCODE_MASK_H34C, tecaputd, anyware_inst },
|
|
{"neaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000660, OPCODE_MASK_H34C, neaputd, anyware_inst },
|
|
{"tneaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0006E0, OPCODE_MASK_H34C, tneaputd, anyware_inst },
|
|
{"necaputd", INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd, anyware_inst },
|
|
{"tnecaputd", INST_TYPE_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
|
|
{"", 0, 0, 0, 0, 0, 0, 0, 0},
|
|
};
|
|
|
|
/* prefix for register names */
|
|
char register_prefix[] = "r";
|
|
char special_register_prefix[] = "spr";
|
|
char fsl_register_prefix[] = "rfsl";
|
|
char pvr_register_prefix[] = "rpvr";
|
|
|
|
|
|
/* #defines for valid immediate range */
|
|
#define MIN_IMM ((int) 0x80000000)
|
|
#define MAX_IMM ((int) 0x7fffffff)
|
|
|
|
#define MIN_IMM15 ((int) 0x0000)
|
|
#define MAX_IMM15 ((int) 0x7fff)
|
|
|
|
#endif /* MICROBLAZE_OPC */
|
|
|
|
#include "dis-asm.h"
|
|
#include <strings.h>
|
|
|
|
#define get_field_rd(instr) get_field(instr, RD_MASK, RD_LOW)
|
|
#define get_field_r1(instr) get_field(instr, RA_MASK, RA_LOW)
|
|
#define get_field_r2(instr) get_field(instr, RB_MASK, RB_LOW)
|
|
#define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW)
|
|
#define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW)
|
|
|
|
/* Local function prototypes. */
|
|
|
|
static char * get_field (long instr, long mask, unsigned short low);
|
|
static char * get_field_imm (long instr);
|
|
static char * get_field_imm5 (long instr);
|
|
static char * get_field_rfsl (long instr);
|
|
static char * get_field_imm15 (long instr);
|
|
#if 0
|
|
static char * get_field_unsigned_imm (long instr);
|
|
#endif
|
|
char * get_field_special (long instr, struct op_code_struct * op);
|
|
unsigned long read_insn_microblaze (bfd_vma memaddr,
|
|
struct disassemble_info *info,
|
|
struct op_code_struct **opr);
|
|
enum microblaze_instr get_insn_microblaze (long inst,
|
|
bfd_boolean *isunsignedimm,
|
|
enum microblaze_instr_type *insn_type,
|
|
short *delay_slots);
|
|
short get_delay_slots_microblaze (long inst);
|
|
enum microblaze_instr microblaze_decode_insn (long insn,
|
|
int *rd,
|
|
int *ra,
|
|
int *rb,
|
|
int *imm);
|
|
unsigned long
|
|
microblaze_get_target_address (long inst,
|
|
bfd_boolean immfound,
|
|
int immval,
|
|
long pcval,
|
|
long r1val,
|
|
long r2val,
|
|
bfd_boolean *targetvalid,
|
|
bfd_boolean *unconditionalbranch);
|
|
|
|
static char *
|
|
get_field (long instr, long mask, unsigned short low)
|
|
{
|
|
char tmpstr[25];
|
|
sprintf(tmpstr, "%s%d", register_prefix, (int)((instr & mask) >> low));
|
|
return(strdup(tmpstr));
|
|
}
|
|
|
|
static char *
|
|
get_field_imm (long instr)
|
|
{
|
|
char tmpstr[25];
|
|
sprintf(tmpstr, "%d", (short)((instr & IMM_MASK) >> IMM_LOW));
|
|
return(strdup(tmpstr));
|
|
}
|
|
|
|
static char *
|
|
get_field_imm5 (long instr)
|
|
{
|
|
char tmpstr[25];
|
|
sprintf(tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
|
|
return(strdup(tmpstr));
|
|
}
|
|
|
|
static char *
|
|
get_field_rfsl (long instr)
|
|
{
|
|
char tmpstr[25];
|
|
sprintf(tmpstr, "%s%d", fsl_register_prefix, (short)((instr & RFSL_MASK) >> IMM_LOW));
|
|
return(strdup(tmpstr));
|
|
}
|
|
|
|
static char *
|
|
get_field_imm15 (long instr)
|
|
{
|
|
char tmpstr[25];
|
|
sprintf(tmpstr, "%d", (short)((instr & IMM15_MASK) >> IMM_LOW));
|
|
return(strdup(tmpstr));
|
|
}
|
|
|
|
#if 0
|
|
static char *
|
|
get_field_unsigned_imm (long instr)
|
|
{
|
|
char tmpstr[25];
|
|
sprintf(tmpstr, "%d", (int)((instr & IMM_MASK) >> IMM_LOW));
|
|
return(strdup(tmpstr));
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
char *
|
|
get_field_special (instr)
|
|
long instr;
|
|
{
|
|
char tmpstr[25];
|
|
|
|
sprintf(tmpstr, "%s%s", register_prefix, (((instr & IMM_MASK) >> IMM_LOW) & REG_MSR_MASK) == 0 ? "pc" : "msr");
|
|
|
|
return(strdup(tmpstr));
|
|
}
|
|
*/
|
|
|
|
char *
|
|
get_field_special (long instr, struct op_code_struct * op)
|
|
{
|
|
char tmpstr[25];
|
|
char spr[6];
|
|
|
|
switch ( (((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) ) {
|
|
|
|
case REG_MSR_MASK :
|
|
strcpy(spr, "msr");
|
|
break;
|
|
case REG_PC_MASK :
|
|
strcpy(spr, "pc");
|
|
break;
|
|
case REG_EAR_MASK :
|
|
strcpy(spr, "ear");
|
|
break;
|
|
case REG_ESR_MASK :
|
|
strcpy(spr, "esr");
|
|
break;
|
|
case REG_FSR_MASK :
|
|
strcpy(spr, "fsr");
|
|
break;
|
|
case REG_BTR_MASK :
|
|
strcpy(spr, "btr");
|
|
break;
|
|
case REG_EDR_MASK :
|
|
strcpy(spr, "edr");
|
|
break;
|
|
case REG_PID_MASK :
|
|
strcpy(spr, "pid");
|
|
break;
|
|
case REG_ZPR_MASK :
|
|
strcpy(spr, "zpr");
|
|
break;
|
|
case REG_TLBX_MASK :
|
|
strcpy(spr, "tlbx");
|
|
break;
|
|
case REG_TLBLO_MASK :
|
|
strcpy(spr, "tlblo");
|
|
break;
|
|
case REG_TLBHI_MASK :
|
|
strcpy(spr, "tlbhi");
|
|
break;
|
|
case REG_TLBSX_MASK :
|
|
strcpy(spr, "tlbsx");
|
|
break;
|
|
default :
|
|
{
|
|
if ( ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000) == REG_PVR_MASK) {
|
|
sprintf(tmpstr, "%spvr%d", register_prefix, (unsigned short)(((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) ^ REG_PVR_MASK);
|
|
return(strdup(tmpstr));
|
|
} else {
|
|
strcpy(spr, "pc");
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
sprintf(tmpstr, "%s%s", register_prefix, spr);
|
|
return(strdup(tmpstr));
|
|
}
|
|
|
|
unsigned long
|
|
read_insn_microblaze (bfd_vma memaddr,
|
|
struct disassemble_info *info,
|
|
struct op_code_struct **opr)
|
|
{
|
|
unsigned char ibytes[4];
|
|
int status;
|
|
struct op_code_struct * op;
|
|
unsigned long inst;
|
|
|
|
status = info->read_memory_func (memaddr, ibytes, 4, info);
|
|
|
|
if (status != 0)
|
|
{
|
|
info->memory_error_func (status, memaddr, info);
|
|
return 0;
|
|
}
|
|
|
|
if (info->endian == BFD_ENDIAN_BIG)
|
|
inst = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | ibytes[3];
|
|
else if (info->endian == BFD_ENDIAN_LITTLE)
|
|
inst = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | ibytes[0];
|
|
else
|
|
abort ();
|
|
|
|
/* Just a linear search of the table. */
|
|
for (op = opcodes; op->name != 0; op ++)
|
|
if (op->bit_sequence == (inst & op->opcode_mask))
|
|
break;
|
|
|
|
*opr = op;
|
|
return inst;
|
|
}
|
|
|
|
|
|
int
|
|
print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
|
|
{
|
|
fprintf_ftype fprintf_func = info->fprintf_func;
|
|
void * stream = info->stream;
|
|
unsigned long inst, prev_inst;
|
|
struct op_code_struct * op, *pop;
|
|
int immval = 0;
|
|
bfd_boolean immfound = FALSE;
|
|
static bfd_vma prev_insn_addr = -1; /*init the prev insn addr */
|
|
static int prev_insn_vma = -1; /*init the prev insn vma */
|
|
int curr_insn_vma = info->buffer_vma;
|
|
|
|
info->bytes_per_chunk = 4;
|
|
|
|
inst = read_insn_microblaze (memaddr, info, &op);
|
|
if (inst == 0) {
|
|
return -1;
|
|
}
|
|
|
|
if (prev_insn_vma == curr_insn_vma) {
|
|
if (memaddr-(info->bytes_per_chunk) == prev_insn_addr) {
|
|
prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
|
|
if (prev_inst == 0)
|
|
return -1;
|
|
if (pop->instr == imm) {
|
|
immval = (get_int_field_imm(prev_inst) << 16) & 0xffff0000;
|
|
immfound = TRUE;
|
|
}
|
|
else {
|
|
immval = 0;
|
|
immfound = FALSE;
|
|
}
|
|
}
|
|
}
|
|
/* make curr insn as prev insn */
|
|
prev_insn_addr = memaddr;
|
|
prev_insn_vma = curr_insn_vma;
|
|
|
|
if (op->name == 0) {
|
|
fprintf_func (stream, ".short 0x%04lx", inst);
|
|
}
|
|
else
|
|
{
|
|
fprintf_func (stream, "%s", op->name);
|
|
|
|
switch (op->inst_type)
|
|
{
|
|
case INST_TYPE_RD_R1_R2:
|
|
fprintf_func(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_r2(inst));
|
|
break;
|
|
case INST_TYPE_RD_R1_IMM:
|
|
fprintf_func(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_imm(inst));
|
|
if (info->print_address_func && get_int_field_r1(inst) == 0 && info->symbol_at_address_func) {
|
|
if (immfound)
|
|
immval |= (get_int_field_imm(inst) & 0x0000ffff);
|
|
else {
|
|
immval = get_int_field_imm(inst);
|
|
if (immval & 0x8000)
|
|
immval |= 0xFFFF0000;
|
|
}
|
|
if (immval > 0 && info->symbol_at_address_func(immval, info)) {
|
|
fprintf_func (stream, "\t// ");
|
|
info->print_address_func (immval, info);
|
|
}
|
|
}
|
|
break;
|
|
case INST_TYPE_RD_R1_IMM5:
|
|
fprintf_func(stream, "\t%s, %s, %s", get_field_rd(inst), get_field_r1(inst), get_field_imm5(inst));
|
|
break;
|
|
case INST_TYPE_RD_RFSL:
|
|
fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_rfsl(inst));
|
|
break;
|
|
case INST_TYPE_R1_RFSL:
|
|
fprintf_func(stream, "\t%s, %s", get_field_r1(inst), get_field_rfsl(inst));
|
|
break;
|
|
case INST_TYPE_RD_SPECIAL:
|
|
fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_special(inst, op));
|
|
break;
|
|
case INST_TYPE_SPECIAL_R1:
|
|
fprintf_func(stream, "\t%s, %s", get_field_special(inst, op), get_field_r1(inst));
|
|
break;
|
|
case INST_TYPE_RD_R1:
|
|
fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_r1(inst));
|
|
break;
|
|
case INST_TYPE_R1_R2:
|
|
fprintf_func(stream, "\t%s, %s", get_field_r1(inst), get_field_r2(inst));
|
|
break;
|
|
case INST_TYPE_R1_IMM:
|
|
fprintf_func(stream, "\t%s, %s", get_field_r1(inst), get_field_imm(inst));
|
|
/* The non-pc relative instructions are returns, which shouldn't
|
|
have a label printed */
|
|
if (info->print_address_func && op->inst_offset_type == INST_PC_OFFSET && info->symbol_at_address_func) {
|
|
if (immfound)
|
|
immval |= (get_int_field_imm(inst) & 0x0000ffff);
|
|
else {
|
|
immval = get_int_field_imm(inst);
|
|
if (immval & 0x8000)
|
|
immval |= 0xFFFF0000;
|
|
}
|
|
immval += memaddr;
|
|
if (immval > 0 && info->symbol_at_address_func(immval, info)) {
|
|
fprintf_func (stream, "\t// ");
|
|
info->print_address_func (immval, info);
|
|
} else {
|
|
fprintf_func (stream, "\t\t// ");
|
|
fprintf_func (stream, "%x", immval);
|
|
}
|
|
}
|
|
break;
|
|
case INST_TYPE_RD_IMM:
|
|
fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_imm(inst));
|
|
if (info->print_address_func && info->symbol_at_address_func) {
|
|
if (immfound)
|
|
immval |= (get_int_field_imm(inst) & 0x0000ffff);
|
|
else {
|
|
immval = get_int_field_imm(inst);
|
|
if (immval & 0x8000)
|
|
immval |= 0xFFFF0000;
|
|
}
|
|
if (op->inst_offset_type == INST_PC_OFFSET)
|
|
immval += (int) memaddr;
|
|
if (info->symbol_at_address_func(immval, info)) {
|
|
fprintf_func (stream, "\t// ");
|
|
info->print_address_func (immval, info);
|
|
}
|
|
}
|
|
break;
|
|
case INST_TYPE_IMM:
|
|
fprintf_func(stream, "\t%s", get_field_imm(inst));
|
|
if (info->print_address_func && info->symbol_at_address_func && op->instr != imm) {
|
|
if (immfound)
|
|
immval |= (get_int_field_imm(inst) & 0x0000ffff);
|
|
else {
|
|
immval = get_int_field_imm(inst);
|
|
if (immval & 0x8000)
|
|
immval |= 0xFFFF0000;
|
|
}
|
|
if (op->inst_offset_type == INST_PC_OFFSET)
|
|
immval += (int) memaddr;
|
|
if (immval > 0 && info->symbol_at_address_func(immval, info)) {
|
|
fprintf_func (stream, "\t// ");
|
|
info->print_address_func (immval, info);
|
|
} else if (op->inst_offset_type == INST_PC_OFFSET) {
|
|
fprintf_func (stream, "\t\t// ");
|
|
fprintf_func (stream, "%x", immval);
|
|
}
|
|
}
|
|
break;
|
|
case INST_TYPE_RD_R2:
|
|
fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_r2(inst));
|
|
break;
|
|
case INST_TYPE_R2:
|
|
fprintf_func(stream, "\t%s", get_field_r2(inst));
|
|
break;
|
|
case INST_TYPE_R1:
|
|
fprintf_func(stream, "\t%s", get_field_r1(inst));
|
|
break;
|
|
case INST_TYPE_RD_R1_SPECIAL:
|
|
fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_r2(inst));
|
|
break;
|
|
case INST_TYPE_RD_IMM15:
|
|
fprintf_func(stream, "\t%s, %s", get_field_rd(inst), get_field_imm15(inst));
|
|
break;
|
|
/* For tuqula instruction */
|
|
case INST_TYPE_RD:
|
|
fprintf_func(stream, "\t%s", get_field_rd(inst));
|
|
break;
|
|
case INST_TYPE_RFSL:
|
|
fprintf_func(stream, "\t%s", get_field_rfsl(inst));
|
|
break;
|
|
default:
|
|
/* if the disassembler lags the instruction set */
|
|
fprintf_func (stream, "\tundecoded operands, inst is 0x%04lx", inst);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Say how many bytes we consumed? */
|
|
return 4;
|
|
}
|
|
|
|
enum microblaze_instr
|
|
get_insn_microblaze (long inst,
|
|
bfd_boolean *isunsignedimm,
|
|
enum microblaze_instr_type *insn_type,
|
|
short *delay_slots)
|
|
{
|
|
struct op_code_struct * op;
|
|
*isunsignedimm = FALSE;
|
|
|
|
/* Just a linear search of the table. */
|
|
for (op = opcodes; op->name != 0; op ++)
|
|
if (op->bit_sequence == (inst & op->opcode_mask))
|
|
break;
|
|
|
|
if (op->name == 0)
|
|
return invalid_inst;
|
|
else {
|
|
*isunsignedimm = (op->inst_type == INST_TYPE_RD_R1_UNSIGNED_IMM);
|
|
*insn_type = op->instr_type;
|
|
*delay_slots = op->delay_slots;
|
|
return op->instr;
|
|
}
|
|
}
|
|
|
|
short
|
|
get_delay_slots_microblaze (long inst)
|
|
{
|
|
bfd_boolean isunsignedimm;
|
|
enum microblaze_instr_type insn_type;
|
|
enum microblaze_instr op;
|
|
short delay_slots;
|
|
|
|
op = get_insn_microblaze( inst, &isunsignedimm, &insn_type, &delay_slots);
|
|
if (op == invalid_inst)
|
|
return 0;
|
|
else
|
|
return delay_slots;
|
|
}
|
|
|
|
enum microblaze_instr
|
|
microblaze_decode_insn (long insn,
|
|
int *rd,
|
|
int *ra,
|
|
int *rb,
|
|
int *imm)
|
|
{
|
|
enum microblaze_instr op;
|
|
bfd_boolean t1;
|
|
enum microblaze_instr_type t2;
|
|
short t3;
|
|
|
|
op = get_insn_microblaze(insn, &t1, &t2, &t3);
|
|
*rd = (insn & RD_MASK) >> RD_LOW;
|
|
*ra = (insn & RA_MASK) >> RA_LOW;
|
|
*rb = (insn & RB_MASK) >> RB_LOW;
|
|
t3 = (insn & IMM_MASK) >> IMM_LOW;
|
|
*imm = (int) t3;
|
|
return (op);
|
|
}
|
|
|
|
unsigned long
|
|
microblaze_get_target_address (long inst,
|
|
bfd_boolean immfound,
|
|
int immval,
|
|
long pcval,
|
|
long r1val,
|
|
long r2val,
|
|
bfd_boolean *targetvalid,
|
|
bfd_boolean *unconditionalbranch)
|
|
{
|
|
struct op_code_struct * op;
|
|
long targetaddr = 0;
|
|
|
|
*unconditionalbranch = FALSE;
|
|
/* Just a linear search of the table. */
|
|
for (op = opcodes; op->name != 0; op ++)
|
|
if (op->bit_sequence == (inst & op->opcode_mask))
|
|
break;
|
|
|
|
if (op->name == 0) {
|
|
*targetvalid = FALSE;
|
|
} else if (op->instr_type == branch_inst) {
|
|
switch (op->inst_type) {
|
|
case INST_TYPE_R2:
|
|
*unconditionalbranch = TRUE;
|
|
/* fallthru */
|
|
case INST_TYPE_RD_R2:
|
|
case INST_TYPE_R1_R2:
|
|
targetaddr = r2val;
|
|
*targetvalid = TRUE;
|
|
if (op->inst_offset_type == INST_PC_OFFSET)
|
|
targetaddr += pcval;
|
|
break;
|
|
case INST_TYPE_IMM:
|
|
*unconditionalbranch = TRUE;
|
|
/* fallthru */
|
|
case INST_TYPE_RD_IMM:
|
|
case INST_TYPE_R1_IMM:
|
|
if (immfound) {
|
|
targetaddr = (immval << 16) & 0xffff0000;
|
|
targetaddr |= (get_int_field_imm(inst) & 0x0000ffff);
|
|
} else {
|
|
targetaddr = get_int_field_imm(inst);
|
|
if (targetaddr & 0x8000)
|
|
targetaddr |= 0xFFFF0000;
|
|
}
|
|
if (op->inst_offset_type == INST_PC_OFFSET)
|
|
targetaddr += pcval;
|
|
*targetvalid = TRUE;
|
|
break;
|
|
default:
|
|
*targetvalid = FALSE;
|
|
break;
|
|
}
|
|
} else if (op->instr_type == return_inst) {
|
|
if (immfound) {
|
|
targetaddr = (immval << 16) & 0xffff0000;
|
|
targetaddr |= (get_int_field_imm(inst) & 0x0000ffff);
|
|
} else {
|
|
targetaddr = get_int_field_imm(inst);
|
|
if (targetaddr & 0x8000)
|
|
targetaddr |= 0xFFFF0000;
|
|
}
|
|
targetaddr += r1val;
|
|
*targetvalid = TRUE;
|
|
} else {
|
|
*targetvalid = FALSE;
|
|
}
|
|
return targetaddr;
|
|
}
|