qemu-e2k/include/hw/riscv
Michael Clark 1e24429e40
SiFive RISC-V PLIC Block
The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stefan O'Rear <sorear2@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
2018-03-07 08:30:28 +13:00
..
riscv_hart.h RISC-V HART Array 2018-03-07 08:30:28 +13:00
riscv_htif.h
sifive_clint.h SiFive RISC-V CLINT Block 2018-03-07 08:30:28 +13:00
sifive_plic.h SiFive RISC-V PLIC Block 2018-03-07 08:30:28 +13:00