ef7716cacc
Commit334c388f25("pflash_cfi: Error out if device length isn't a power of two") aimed to finish the effort started by commit06f1521795("pflash: Require backend size to match device, improve errors"), but unfortunately we are not quite there since various machines are still ready to accept incomplete / oversized pflash backend images, and now fail, i.e. on Debian bullseye: $ qemu-system-x86_64 \ -drive \ if=pflash,format=raw,unit=0,readonly=on,file=/usr/share/OVMF/OVMF_CODE.fd qemu-system-x86_64: Device size must be a power of two. where OVMF_CODE.fd comes from the ovmf package, which doesn't pad the firmware images to the flash size: $ ls -lh /usr/share/OVMF/ -rw-r--r-- 1 root root 3.5M Aug 19 2021 OVMF_CODE_4M.fd -rw-r--r-- 1 root root 1.9M Aug 19 2021 OVMF_CODE.fd -rw-r--r-- 1 root root 128K Aug 19 2021 OVMF_VARS.fd Since we entered the freeze period to prepare the v7.2.0 release, the safest is to revert commit334c388f25. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1294 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221108175755.95141-1-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221108172633.860700-1-danielhb413@gmail.com>
1032 lines
33 KiB
C
1032 lines
33 KiB
C
/*
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* CFI parallel flash with AMD command set emulation
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*
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* Copyright (c) 2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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* Supported commands/modes are:
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* - flash read
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* - flash write
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* - flash ID read
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* - sector erase
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* - chip erase
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* - unlock bypass command
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* - CFI queries
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*
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* It does not support flash interleaving.
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* It does not implement software data protection as found in many real chips
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*/
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#include "qemu/osdep.h"
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#include "hw/block/block.h"
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#include "hw/block/flash.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/bitmap.h"
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#include "qemu/timer.h"
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#include "sysemu/block-backend.h"
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#include "qemu/host-utils.h"
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#include "qemu/module.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#define PFLASH_LAZY_ROMD_THRESHOLD 42
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/*
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* The size of the cfi_table indirectly depends on this and the start of the
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* PRI table directly depends on it. 4 is the maximum size (and also what
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* seems common) without changing the PRT table address.
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*/
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#define PFLASH_MAX_ERASE_REGIONS 4
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/* Special write cycles for CFI queries. */
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enum {
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WCYCLE_CFI = 7,
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WCYCLE_AUTOSELECT_CFI = 8,
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};
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struct PFlashCFI02 {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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BlockBackend *blk;
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uint32_t uniform_nb_blocs;
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uint32_t uniform_sector_len;
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uint32_t total_sectors;
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uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS];
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uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS];
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uint32_t chip_len;
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uint8_t mappings;
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uint8_t width;
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uint8_t be;
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int wcycle; /* if 0, the flash is read normally */
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int bypass;
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int ro;
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uint8_t cmd;
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uint8_t status;
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/* FIXME: implement array device properties */
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uint16_t ident0;
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uint16_t ident1;
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uint16_t ident2;
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uint16_t ident3;
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uint16_t unlock_addr0;
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uint16_t unlock_addr1;
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uint8_t cfi_table[0x4d];
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QEMUTimer timer;
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/*
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* The device replicates the flash memory across its memory space. Emulate
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* that by having a container (.mem) filled with an array of aliases
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* (.mem_mappings) pointing to the flash memory (.orig_mem).
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*/
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MemoryRegion mem;
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MemoryRegion *mem_mappings; /* array; one per mapping */
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MemoryRegion orig_mem;
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bool rom_mode;
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int read_counter; /* used for lazy switch-back to rom mode */
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int sectors_to_erase;
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uint64_t erase_time_remaining;
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unsigned long *sector_erase_map;
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char *name;
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void *storage;
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};
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/*
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* Toggle status bit DQ7.
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*/
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static inline void toggle_dq7(PFlashCFI02 *pfl)
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{
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pfl->status ^= 0x80;
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}
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/*
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* Set status bit DQ7 to bit 7 of value.
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*/
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static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value)
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{
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pfl->status &= 0x7F;
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pfl->status |= value & 0x80;
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}
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/*
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* Toggle status bit DQ6.
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*/
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static inline void toggle_dq6(PFlashCFI02 *pfl)
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{
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pfl->status ^= 0x40;
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}
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/*
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* Turn on DQ3.
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*/
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static inline void assert_dq3(PFlashCFI02 *pfl)
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{
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pfl->status |= 0x08;
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}
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/*
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* Turn off DQ3.
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*/
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static inline void reset_dq3(PFlashCFI02 *pfl)
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{
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pfl->status &= ~0x08;
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}
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/*
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* Toggle status bit DQ2.
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*/
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static inline void toggle_dq2(PFlashCFI02 *pfl)
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{
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pfl->status ^= 0x04;
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}
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/*
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* Set up replicated mappings of the same region.
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*/
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static void pflash_setup_mappings(PFlashCFI02 *pfl)
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{
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unsigned i;
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hwaddr size = memory_region_size(&pfl->orig_mem);
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memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
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pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
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for (i = 0; i < pfl->mappings; ++i) {
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memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
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"pflash-alias", &pfl->orig_mem, 0, size);
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memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
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}
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}
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static void pflash_reset_state_machine(PFlashCFI02 *pfl)
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{
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trace_pflash_reset(pfl->name);
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pfl->cmd = 0x00;
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pfl->wcycle = 0;
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}
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static void pflash_mode_read_array(PFlashCFI02 *pfl)
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{
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trace_pflash_mode_read_array(pfl->name);
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pflash_reset_state_machine(pfl);
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pfl->rom_mode = true;
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memory_region_rom_device_set_romd(&pfl->orig_mem, true);
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}
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static size_t pflash_regions_count(PFlashCFI02 *pfl)
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{
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return pfl->cfi_table[0x2c];
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}
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/*
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* Returns the time it takes to erase the number of sectors scheduled for
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* erasure based on CFI address 0x21 which is "Typical timeout per individual
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* block erase 2^N ms."
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*/
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static uint64_t pflash_erase_time(PFlashCFI02 *pfl)
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{
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/*
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* If there are no sectors to erase (which can happen if all of the sectors
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* to be erased are protected), then erase takes 100 us. Protected sectors
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* aren't supported so this should never happen.
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*/
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return ((1ULL << pfl->cfi_table[0x21]) * pfl->sectors_to_erase) * SCALE_US;
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}
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/*
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* Returns true if the device is currently in erase suspend mode.
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*/
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static inline bool pflash_erase_suspend_mode(PFlashCFI02 *pfl)
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{
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return pfl->erase_time_remaining > 0;
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}
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static void pflash_timer(void *opaque)
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{
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PFlashCFI02 *pfl = opaque;
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trace_pflash_timer_expired(pfl->name, pfl->cmd);
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if (pfl->cmd == 0x30) {
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/*
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* Sector erase. If DQ3 is 0 when the timer expires, then the 50
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* us erase timeout has expired so we need to start the timer for the
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* sector erase algorithm. Otherwise, the erase completed and we should
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* go back to read array mode.
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*/
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if ((pfl->status & 0x08) == 0) {
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assert_dq3(pfl);
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uint64_t timeout = pflash_erase_time(pfl);
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timer_mod(&pfl->timer,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
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trace_pflash_erase_timeout(pfl->name, pfl->sectors_to_erase);
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return;
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}
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trace_pflash_erase_complete(pfl->name);
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bitmap_zero(pfl->sector_erase_map, pfl->total_sectors);
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pfl->sectors_to_erase = 0;
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reset_dq3(pfl);
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}
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/* Reset flash */
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toggle_dq7(pfl);
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if (pfl->bypass) {
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pfl->wcycle = 2;
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pfl->cmd = 0;
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} else {
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pflash_mode_read_array(pfl);
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}
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}
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/*
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* Read data from flash.
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*/
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static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset,
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unsigned int width)
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{
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uint8_t *p = (uint8_t *)pfl->storage + offset;
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uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width);
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trace_pflash_data_read(pfl->name, offset, width, ret);
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return ret;
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}
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typedef struct {
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uint32_t len;
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uint32_t num;
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} SectorInfo;
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/*
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* offset should be a byte offset of the QEMU device and _not_ a device
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* offset.
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*/
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static SectorInfo pflash_sector_info(PFlashCFI02 *pfl, hwaddr offset)
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{
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assert(offset < pfl->chip_len);
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hwaddr addr = 0;
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uint32_t sector_num = 0;
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for (int i = 0; i < pflash_regions_count(pfl); ++i) {
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uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i];
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if (addr <= offset && offset < addr + region_size) {
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return (SectorInfo) {
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.len = pfl->sector_len[i],
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.num = sector_num + (offset - addr) / pfl->sector_len[i],
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};
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}
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sector_num += pfl->nb_blocs[i];
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addr += region_size;
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}
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abort();
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}
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/*
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* Returns true if the offset refers to a flash sector that is currently being
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* erased.
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*/
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static bool pflash_sector_is_erasing(PFlashCFI02 *pfl, hwaddr offset)
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{
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long sector_num = pflash_sector_info(pfl, offset).num;
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return test_bit(sector_num, pfl->sector_erase_map);
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}
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static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
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{
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PFlashCFI02 *pfl = opaque;
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hwaddr boff;
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uint64_t ret;
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/* Lazy reset to ROMD mode after a certain amount of read accesses */
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if (!pfl->rom_mode && pfl->wcycle == 0 &&
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++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
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pflash_mode_read_array(pfl);
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}
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offset &= pfl->chip_len - 1;
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boff = offset & 0xFF;
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if (pfl->width == 2) {
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boff = boff >> 1;
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} else if (pfl->width == 4) {
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boff = boff >> 2;
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}
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switch (pfl->cmd) {
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default:
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/* This should never happen : reset state & treat it as a read*/
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trace_pflash_read_unknown_state(pfl->name, pfl->cmd);
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pflash_reset_state_machine(pfl);
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/* fall through to the read code */
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case 0x80: /* Erase (unlock) */
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/* We accept reads during second unlock sequence... */
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case 0x00:
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if (pflash_erase_suspend_mode(pfl) &&
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pflash_sector_is_erasing(pfl, offset)) {
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/* Toggle bit 2, but not 6. */
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toggle_dq2(pfl);
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/* Status register read */
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ret = pfl->status;
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trace_pflash_read_status(pfl->name, ret);
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break;
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}
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/* Flash area read */
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ret = pflash_data_read(pfl, offset, width);
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break;
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case 0x90: /* flash ID read */
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switch (boff) {
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case 0x00:
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case 0x01:
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ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
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break;
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case 0x02:
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ret = 0x00; /* Pretend all sectors are unprotected */
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break;
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case 0x0E:
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case 0x0F:
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ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
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if (ret != (uint8_t)-1) {
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break;
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}
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/* Fall through to data read. */
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default:
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ret = pflash_data_read(pfl, offset, width);
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}
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trace_pflash_read_done(pfl->name, boff, ret);
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break;
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case 0x10: /* Chip Erase */
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case 0x30: /* Sector Erase */
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/* Toggle bit 2 during erase, but not program. */
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toggle_dq2(pfl);
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/* fall through */
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case 0xA0: /* Program */
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/* Toggle bit 6 */
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toggle_dq6(pfl);
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/* Status register read */
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ret = pfl->status;
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trace_pflash_read_status(pfl->name, ret);
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break;
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case 0x98:
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/* CFI query mode */
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if (boff < sizeof(pfl->cfi_table)) {
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ret = pfl->cfi_table[boff];
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} else {
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ret = 0;
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}
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break;
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}
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trace_pflash_io_read(pfl->name, offset, width, ret, pfl->cmd, pfl->wcycle);
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return ret;
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}
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/* update flash content on disk */
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static void pflash_update(PFlashCFI02 *pfl, int offset, int size)
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{
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int offset_end;
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int ret;
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if (pfl->blk) {
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offset_end = offset + size;
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/* widen to sector boundaries */
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offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
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offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
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ret = blk_pwrite(pfl->blk, offset, offset_end - offset,
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pfl->storage + offset, 0);
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if (ret < 0) {
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/* TODO set error bit in status */
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error_report("Could not update PFLASH: %s", strerror(-ret));
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}
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}
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}
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static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset)
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{
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SectorInfo sector_info = pflash_sector_info(pfl, offset);
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uint64_t sector_len = sector_info.len;
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offset &= ~(sector_len - 1);
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trace_pflash_sector_erase_start(pfl->name, pfl->width * 2, offset,
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pfl->width * 2, offset + sector_len - 1);
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if (!pfl->ro) {
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uint8_t *p = pfl->storage;
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memset(p + offset, 0xff, sector_len);
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pflash_update(pfl, offset, sector_len);
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}
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set_dq7(pfl, 0x00);
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++pfl->sectors_to_erase;
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set_bit(sector_info.num, pfl->sector_erase_map);
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/* Set (or reset) the 50 us timer for additional erase commands. */
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timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000);
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}
|
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|
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static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
|
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unsigned int width)
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{
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PFlashCFI02 *pfl = opaque;
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hwaddr boff;
|
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uint8_t *p;
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uint8_t cmd;
|
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trace_pflash_io_write(pfl->name, offset, width, value, pfl->wcycle);
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cmd = value;
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if (pfl->cmd != 0xA0) {
|
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/* Reset does nothing during chip erase and sector erase. */
|
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if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) {
|
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if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) {
|
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/* Return to autoselect mode. */
|
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pfl->wcycle = 3;
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pfl->cmd = 0x90;
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return;
|
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}
|
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goto reset_flash;
|
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}
|
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}
|
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offset &= pfl->chip_len - 1;
|
|
|
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boff = offset;
|
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if (pfl->width == 2) {
|
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boff = boff >> 1;
|
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} else if (pfl->width == 4) {
|
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boff = boff >> 2;
|
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}
|
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/* Only the least-significant 11 bits are used in most cases. */
|
|
boff &= 0x7FF;
|
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switch (pfl->wcycle) {
|
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case 0:
|
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/* Set the device in I/O access mode if required */
|
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if (pfl->rom_mode) {
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pfl->rom_mode = false;
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memory_region_rom_device_set_romd(&pfl->orig_mem, false);
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}
|
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pfl->read_counter = 0;
|
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/* We're in read mode */
|
|
check_unlock0:
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if (boff == 0x55 && cmd == 0x98) {
|
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/* Enter CFI query mode */
|
|
pfl->wcycle = WCYCLE_CFI;
|
|
pfl->cmd = 0x98;
|
|
return;
|
|
}
|
|
/* Handle erase resume in erase suspend mode, otherwise reset. */
|
|
if (cmd == 0x30) { /* Erase Resume */
|
|
if (pflash_erase_suspend_mode(pfl)) {
|
|
/* Resume the erase. */
|
|
timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
|
|
pfl->erase_time_remaining);
|
|
pfl->erase_time_remaining = 0;
|
|
pfl->wcycle = 6;
|
|
pfl->cmd = 0x30;
|
|
set_dq7(pfl, 0x00);
|
|
assert_dq3(pfl);
|
|
return;
|
|
}
|
|
goto reset_flash;
|
|
}
|
|
/* Ignore erase suspend. */
|
|
if (cmd == 0xB0) { /* Erase Suspend */
|
|
return;
|
|
}
|
|
if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
|
|
trace_pflash_unlock0_failed(pfl->name, boff,
|
|
cmd, pfl->unlock_addr0);
|
|
goto reset_flash;
|
|
}
|
|
trace_pflash_write(pfl->name, "unlock sequence started");
|
|
break;
|
|
case 1:
|
|
/* We started an unlock sequence */
|
|
check_unlock1:
|
|
if (boff != pfl->unlock_addr1 || cmd != 0x55) {
|
|
trace_pflash_unlock1_failed(pfl->name, boff, cmd);
|
|
goto reset_flash;
|
|
}
|
|
trace_pflash_write(pfl->name, "unlock sequence done");
|
|
break;
|
|
case 2:
|
|
/* We finished an unlock sequence */
|
|
if (!pfl->bypass && boff != pfl->unlock_addr0) {
|
|
trace_pflash_write_failed(pfl->name, boff, cmd);
|
|
goto reset_flash;
|
|
}
|
|
switch (cmd) {
|
|
case 0x20:
|
|
pfl->bypass = 1;
|
|
goto do_bypass;
|
|
case 0x80: /* Erase */
|
|
case 0x90: /* Autoselect */
|
|
case 0xA0: /* Program */
|
|
pfl->cmd = cmd;
|
|
trace_pflash_write_start(pfl->name, cmd);
|
|
break;
|
|
default:
|
|
trace_pflash_write_unknown(pfl->name, cmd);
|
|
goto reset_flash;
|
|
}
|
|
break;
|
|
case 3:
|
|
switch (pfl->cmd) {
|
|
case 0x80: /* Erase */
|
|
/* We need another unlock sequence */
|
|
goto check_unlock0;
|
|
case 0xA0: /* Program */
|
|
if (pflash_erase_suspend_mode(pfl) &&
|
|
pflash_sector_is_erasing(pfl, offset)) {
|
|
/* Ignore writes to erasing sectors. */
|
|
if (pfl->bypass) {
|
|
goto do_bypass;
|
|
}
|
|
goto reset_flash;
|
|
}
|
|
trace_pflash_data_write(pfl->name, offset, width, value, 0);
|
|
if (!pfl->ro) {
|
|
p = (uint8_t *)pfl->storage + offset;
|
|
if (pfl->be) {
|
|
uint64_t current = ldn_be_p(p, width);
|
|
stn_be_p(p, width, current & value);
|
|
} else {
|
|
uint64_t current = ldn_le_p(p, width);
|
|
stn_le_p(p, width, current & value);
|
|
}
|
|
pflash_update(pfl, offset, width);
|
|
}
|
|
/*
|
|
* While programming, status bit DQ7 should hold the opposite
|
|
* value from how it was programmed.
|
|
*/
|
|
set_dq7(pfl, ~value);
|
|
/* Let's pretend write is immediate */
|
|
if (pfl->bypass)
|
|
goto do_bypass;
|
|
goto reset_flash;
|
|
case 0x90: /* Autoselect */
|
|
if (pfl->bypass && cmd == 0x00) {
|
|
/* Unlock bypass reset */
|
|
goto reset_flash;
|
|
}
|
|
/*
|
|
* We can enter CFI query mode from autoselect mode, but we must
|
|
* return to autoselect mode after a reset.
|
|
*/
|
|
if (boff == 0x55 && cmd == 0x98) {
|
|
/* Enter autoselect CFI query mode */
|
|
pfl->wcycle = WCYCLE_AUTOSELECT_CFI;
|
|
pfl->cmd = 0x98;
|
|
return;
|
|
}
|
|
/* fall through */
|
|
default:
|
|
trace_pflash_write_invalid(pfl->name, pfl->cmd);
|
|
goto reset_flash;
|
|
}
|
|
case 4:
|
|
switch (pfl->cmd) {
|
|
case 0xA0: /* Program */
|
|
/* Ignore writes while flash data write is occurring */
|
|
/* As we suppose write is immediate, this should never happen */
|
|
return;
|
|
case 0x80: /* Erase */
|
|
goto check_unlock1;
|
|
default:
|
|
/* Should never happen */
|
|
trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 5);
|
|
goto reset_flash;
|
|
}
|
|
break;
|
|
case 5:
|
|
if (pflash_erase_suspend_mode(pfl)) {
|
|
/* Erasing is not supported in erase suspend mode. */
|
|
goto reset_flash;
|
|
}
|
|
switch (cmd) {
|
|
case 0x10: /* Chip Erase */
|
|
if (boff != pfl->unlock_addr0) {
|
|
trace_pflash_chip_erase_invalid(pfl->name, offset);
|
|
goto reset_flash;
|
|
}
|
|
/* Chip erase */
|
|
trace_pflash_chip_erase_start(pfl->name);
|
|
if (!pfl->ro) {
|
|
memset(pfl->storage, 0xff, pfl->chip_len);
|
|
pflash_update(pfl, 0, pfl->chip_len);
|
|
}
|
|
set_dq7(pfl, 0x00);
|
|
/* Wait the time specified at CFI address 0x22. */
|
|
timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
|
|
(1ULL << pfl->cfi_table[0x22]) * SCALE_MS);
|
|
break;
|
|
case 0x30: /* Sector erase */
|
|
pflash_sector_erase(pfl, offset);
|
|
break;
|
|
default:
|
|
trace_pflash_write_invalid_command(pfl->name, cmd);
|
|
goto reset_flash;
|
|
}
|
|
pfl->cmd = cmd;
|
|
break;
|
|
case 6:
|
|
switch (pfl->cmd) {
|
|
case 0x10: /* Chip Erase */
|
|
/* Ignore writes during chip erase */
|
|
return;
|
|
case 0x30: /* Sector erase */
|
|
if (cmd == 0xB0) {
|
|
/*
|
|
* If erase suspend happens during the erase timeout (so DQ3 is
|
|
* 0), then the device suspends erasing immediately. Set the
|
|
* remaining time to be the total time to erase. Otherwise,
|
|
* there is a maximum amount of time it can take to enter
|
|
* suspend mode. Let's ignore that and suspend immediately and
|
|
* set the remaining time to the actual time remaining on the
|
|
* timer.
|
|
*/
|
|
if ((pfl->status & 0x08) == 0) {
|
|
pfl->erase_time_remaining = pflash_erase_time(pfl);
|
|
} else {
|
|
int64_t delta = timer_expire_time_ns(&pfl->timer) -
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
|
/* Make sure we have a positive time remaining. */
|
|
pfl->erase_time_remaining = delta <= 0 ? 1 : delta;
|
|
}
|
|
reset_dq3(pfl);
|
|
timer_del(&pfl->timer);
|
|
pflash_reset_state_machine(pfl);
|
|
return;
|
|
}
|
|
/*
|
|
* If DQ3 is 0, additional sector erase commands can be
|
|
* written and anything else (other than an erase suspend) resets
|
|
* the device.
|
|
*/
|
|
if ((pfl->status & 0x08) == 0) {
|
|
if (cmd == 0x30) {
|
|
pflash_sector_erase(pfl, offset);
|
|
} else {
|
|
goto reset_flash;
|
|
}
|
|
}
|
|
/* Ignore writes during the actual erase. */
|
|
return;
|
|
default:
|
|
/* Should never happen */
|
|
trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 6);
|
|
goto reset_flash;
|
|
}
|
|
break;
|
|
/* Special values for CFI queries */
|
|
case WCYCLE_CFI:
|
|
case WCYCLE_AUTOSELECT_CFI:
|
|
trace_pflash_write(pfl->name, "invalid write in CFI query mode");
|
|
goto reset_flash;
|
|
default:
|
|
/* Should never happen */
|
|
trace_pflash_write(pfl->name, "invalid write state (wc 7)");
|
|
goto reset_flash;
|
|
}
|
|
pfl->wcycle++;
|
|
|
|
return;
|
|
|
|
/* Reset flash */
|
|
reset_flash:
|
|
pfl->bypass = 0;
|
|
pflash_reset_state_machine(pfl);
|
|
return;
|
|
|
|
do_bypass:
|
|
pfl->wcycle = 2;
|
|
pfl->cmd = 0;
|
|
}
|
|
|
|
static const MemoryRegionOps pflash_cfi02_ops = {
|
|
.read = pflash_read,
|
|
.write = pflash_write,
|
|
.valid.min_access_size = 1,
|
|
.valid.max_access_size = 4,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void pflash_cfi02_fill_cfi_table(PFlashCFI02 *pfl, int nb_regions)
|
|
{
|
|
/* Hardcoded CFI table (mostly from SG29 Spansion flash) */
|
|
const uint16_t pri_ofs = 0x40;
|
|
/* Standard "QRY" string */
|
|
pfl->cfi_table[0x10] = 'Q';
|
|
pfl->cfi_table[0x11] = 'R';
|
|
pfl->cfi_table[0x12] = 'Y';
|
|
/* Command set (AMD/Fujitsu) */
|
|
pfl->cfi_table[0x13] = 0x02;
|
|
pfl->cfi_table[0x14] = 0x00;
|
|
/* Primary extended table address */
|
|
pfl->cfi_table[0x15] = pri_ofs;
|
|
pfl->cfi_table[0x16] = pri_ofs >> 8;
|
|
/* Alternate command set (none) */
|
|
pfl->cfi_table[0x17] = 0x00;
|
|
pfl->cfi_table[0x18] = 0x00;
|
|
/* Alternate extended table (none) */
|
|
pfl->cfi_table[0x19] = 0x00;
|
|
pfl->cfi_table[0x1A] = 0x00;
|
|
/* Vcc min */
|
|
pfl->cfi_table[0x1B] = 0x27;
|
|
/* Vcc max */
|
|
pfl->cfi_table[0x1C] = 0x36;
|
|
/* Vpp min (no Vpp pin) */
|
|
pfl->cfi_table[0x1D] = 0x00;
|
|
/* Vpp max (no Vpp pin) */
|
|
pfl->cfi_table[0x1E] = 0x00;
|
|
/* Timeout per single byte/word write (128 ms) */
|
|
pfl->cfi_table[0x1F] = 0x07;
|
|
/* Timeout for min size buffer write (NA) */
|
|
pfl->cfi_table[0x20] = 0x00;
|
|
/* Typical timeout for block erase (512 ms) */
|
|
pfl->cfi_table[0x21] = 0x09;
|
|
/* Typical timeout for full chip erase (4096 ms) */
|
|
pfl->cfi_table[0x22] = 0x0C;
|
|
/* Reserved */
|
|
pfl->cfi_table[0x23] = 0x01;
|
|
/* Max timeout for buffer write (NA) */
|
|
pfl->cfi_table[0x24] = 0x00;
|
|
/* Max timeout for block erase */
|
|
pfl->cfi_table[0x25] = 0x0A;
|
|
/* Max timeout for chip erase */
|
|
pfl->cfi_table[0x26] = 0x0D;
|
|
/* Device size */
|
|
pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
|
|
/* Flash device interface (8 & 16 bits) */
|
|
pfl->cfi_table[0x28] = 0x02;
|
|
pfl->cfi_table[0x29] = 0x00;
|
|
/* Max number of bytes in multi-bytes write */
|
|
/*
|
|
* XXX: disable buffered write as it's not supported
|
|
* pfl->cfi_table[0x2A] = 0x05;
|
|
*/
|
|
pfl->cfi_table[0x2A] = 0x00;
|
|
pfl->cfi_table[0x2B] = 0x00;
|
|
/* Number of erase block regions */
|
|
pfl->cfi_table[0x2c] = nb_regions;
|
|
/* Erase block regions */
|
|
for (int i = 0; i < nb_regions; ++i) {
|
|
uint32_t sector_len_per_device = pfl->sector_len[i];
|
|
pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
|
|
pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
|
|
pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
|
|
pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
|
|
}
|
|
assert(0x2c + 4 * nb_regions < pri_ofs);
|
|
|
|
/* Extended */
|
|
pfl->cfi_table[0x00 + pri_ofs] = 'P';
|
|
pfl->cfi_table[0x01 + pri_ofs] = 'R';
|
|
pfl->cfi_table[0x02 + pri_ofs] = 'I';
|
|
|
|
/* Extended version 1.0 */
|
|
pfl->cfi_table[0x03 + pri_ofs] = '1';
|
|
pfl->cfi_table[0x04 + pri_ofs] = '0';
|
|
|
|
/* Address sensitive unlock required. */
|
|
pfl->cfi_table[0x05 + pri_ofs] = 0x00;
|
|
/* Erase suspend to read/write. */
|
|
pfl->cfi_table[0x06 + pri_ofs] = 0x02;
|
|
/* Sector protect not supported. */
|
|
pfl->cfi_table[0x07 + pri_ofs] = 0x00;
|
|
/* Temporary sector unprotect not supported. */
|
|
pfl->cfi_table[0x08 + pri_ofs] = 0x00;
|
|
|
|
/* Sector protect/unprotect scheme. */
|
|
pfl->cfi_table[0x09 + pri_ofs] = 0x00;
|
|
|
|
/* Simultaneous operation not supported. */
|
|
pfl->cfi_table[0x0a + pri_ofs] = 0x00;
|
|
/* Burst mode not supported. */
|
|
pfl->cfi_table[0x0b + pri_ofs] = 0x00;
|
|
/* Page mode not supported. */
|
|
pfl->cfi_table[0x0c + pri_ofs] = 0x00;
|
|
assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
|
|
}
|
|
|
|
static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
ERRP_GUARD();
|
|
PFlashCFI02 *pfl = PFLASH_CFI02(dev);
|
|
int ret;
|
|
|
|
if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) {
|
|
error_setg(errp, "attribute \"sector-length\" not specified or zero.");
|
|
return;
|
|
}
|
|
if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) {
|
|
error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
|
|
return;
|
|
}
|
|
if (pfl->name == NULL) {
|
|
error_setg(errp, "attribute \"name\" not specified.");
|
|
return;
|
|
}
|
|
|
|
int nb_regions;
|
|
pfl->chip_len = 0;
|
|
pfl->total_sectors = 0;
|
|
for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) {
|
|
if (pfl->nb_blocs[nb_regions] == 0) {
|
|
break;
|
|
}
|
|
pfl->total_sectors += pfl->nb_blocs[nb_regions];
|
|
uint64_t sector_len_per_device = pfl->sector_len[nb_regions];
|
|
|
|
/*
|
|
* The size of each flash sector must be a power of 2 and it must be
|
|
* aligned at the same power of 2.
|
|
*/
|
|
if (sector_len_per_device & 0xff ||
|
|
sector_len_per_device >= (1 << 24) ||
|
|
!is_power_of_2(sector_len_per_device))
|
|
{
|
|
error_setg(errp, "unsupported configuration: "
|
|
"sector length[%d] per device = %" PRIx64 ".",
|
|
nb_regions, sector_len_per_device);
|
|
return;
|
|
}
|
|
if (pfl->chip_len & (sector_len_per_device - 1)) {
|
|
error_setg(errp, "unsupported configuration: "
|
|
"flash region %d not correctly aligned.",
|
|
nb_regions);
|
|
return;
|
|
}
|
|
|
|
pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] *
|
|
pfl->nb_blocs[nb_regions];
|
|
}
|
|
|
|
uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs *
|
|
pfl->uniform_sector_len;
|
|
if (nb_regions == 0) {
|
|
nb_regions = 1;
|
|
pfl->nb_blocs[0] = pfl->uniform_nb_blocs;
|
|
pfl->sector_len[0] = pfl->uniform_sector_len;
|
|
pfl->chip_len = uniform_len;
|
|
pfl->total_sectors = pfl->uniform_nb_blocs;
|
|
} else if (uniform_len != 0 && uniform_len != pfl->chip_len) {
|
|
error_setg(errp, "\"num-blocks\"*\"sector-length\" "
|
|
"different from \"num-blocks0\"*\'sector-length0\" + ... + "
|
|
"\"num-blocks3\"*\"sector-length3\"");
|
|
return;
|
|
}
|
|
|
|
memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl),
|
|
&pflash_cfi02_ops, pfl, pfl->name,
|
|
pfl->chip_len, errp);
|
|
if (*errp) {
|
|
return;
|
|
}
|
|
|
|
pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
|
|
|
|
if (pfl->blk) {
|
|
uint64_t perm;
|
|
pfl->ro = !blk_supports_write_perm(pfl->blk);
|
|
perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
|
|
ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
|
|
if (ret < 0) {
|
|
return;
|
|
}
|
|
} else {
|
|
pfl->ro = 0;
|
|
}
|
|
|
|
if (pfl->blk) {
|
|
if (!blk_check_size_and_read_all(pfl->blk, pfl->storage,
|
|
pfl->chip_len, errp)) {
|
|
vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Only 11 bits are used in the comparison. */
|
|
pfl->unlock_addr0 &= 0x7FF;
|
|
pfl->unlock_addr1 &= 0x7FF;
|
|
|
|
/* Allocate memory for a bitmap for sectors being erased. */
|
|
pfl->sector_erase_map = bitmap_new(pfl->total_sectors);
|
|
|
|
pfl->rom_mode = true;
|
|
if (pfl->mappings > 1) {
|
|
pflash_setup_mappings(pfl);
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
|
|
} else {
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->orig_mem);
|
|
}
|
|
|
|
timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
|
|
pfl->status = 0;
|
|
|
|
pflash_cfi02_fill_cfi_table(pfl, nb_regions);
|
|
}
|
|
|
|
static void pflash_cfi02_reset(DeviceState *dev)
|
|
{
|
|
PFlashCFI02 *pfl = PFLASH_CFI02(dev);
|
|
|
|
pflash_reset_state_machine(pfl);
|
|
}
|
|
|
|
static Property pflash_cfi02_properties[] = {
|
|
DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
|
|
DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0),
|
|
DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0),
|
|
DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0),
|
|
DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0),
|
|
DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0),
|
|
DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0),
|
|
DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0),
|
|
DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0),
|
|
DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0),
|
|
DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0),
|
|
DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
|
|
DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
|
|
DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
|
|
DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
|
|
DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
|
|
DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
|
|
DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
|
|
DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
|
|
DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
|
|
DEFINE_PROP_STRING("name", PFlashCFI02, name),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void pflash_cfi02_unrealize(DeviceState *dev)
|
|
{
|
|
PFlashCFI02 *pfl = PFLASH_CFI02(dev);
|
|
timer_del(&pfl->timer);
|
|
g_free(pfl->sector_erase_map);
|
|
}
|
|
|
|
static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = pflash_cfi02_realize;
|
|
dc->reset = pflash_cfi02_reset;
|
|
dc->unrealize = pflash_cfi02_unrealize;
|
|
device_class_set_props(dc, pflash_cfi02_properties);
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
|
}
|
|
|
|
static const TypeInfo pflash_cfi02_info = {
|
|
.name = TYPE_PFLASH_CFI02,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(PFlashCFI02),
|
|
.class_init = pflash_cfi02_class_init,
|
|
};
|
|
|
|
static void pflash_cfi02_register_types(void)
|
|
{
|
|
type_register_static(&pflash_cfi02_info);
|
|
}
|
|
|
|
type_init(pflash_cfi02_register_types)
|
|
|
|
PFlashCFI02 *pflash_cfi02_register(hwaddr base,
|
|
const char *name,
|
|
hwaddr size,
|
|
BlockBackend *blk,
|
|
uint32_t sector_len,
|
|
int nb_mappings, int width,
|
|
uint16_t id0, uint16_t id1,
|
|
uint16_t id2, uint16_t id3,
|
|
uint16_t unlock_addr0,
|
|
uint16_t unlock_addr1,
|
|
int be)
|
|
{
|
|
DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02);
|
|
|
|
if (blk) {
|
|
qdev_prop_set_drive(dev, "drive", blk);
|
|
}
|
|
assert(QEMU_IS_ALIGNED(size, sector_len));
|
|
qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
|
|
qdev_prop_set_uint32(dev, "sector-length", sector_len);
|
|
qdev_prop_set_uint8(dev, "width", width);
|
|
qdev_prop_set_uint8(dev, "mappings", nb_mappings);
|
|
qdev_prop_set_uint8(dev, "big-endian", !!be);
|
|
qdev_prop_set_uint16(dev, "id0", id0);
|
|
qdev_prop_set_uint16(dev, "id1", id1);
|
|
qdev_prop_set_uint16(dev, "id2", id2);
|
|
qdev_prop_set_uint16(dev, "id3", id3);
|
|
qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
|
|
qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
|
|
qdev_prop_set_string(dev, "name", name);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
|
|
return PFLASH_CFI02(dev);
|
|
}
|